research-article

Packing Techniques for Virtex-5 FPGAs

Authors:

Paul D. Kundarewich,

Jason H. AndersonAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 2, Issue 3

Article No.: 18, Pages 1 - 24

https://doi.org/10.1145/1575774.1575777

Published: 01 September 2009 Publication History

Abstract

Packing is a key step in the FPGA tool flow that straddles the boundaries between synthesis, technology mapping and placement. Packing strongly influences circuit speed, density, and power, and in this article, we consider packing in the commercial FPGA context and examine the area and performance trade-offs associated with packing in a state-of-the-art FPGA---the Xilinx^® Virtex^TM-5 FPGA. In addition to look-up-table (LUT)-based logic blocks, modern FPGAs also contain large IP blocks. We discuss packing techniques for both types of blocks. Virtex-5 logic blocks contain dual-output 6-input LUTs. Such LUTs can implement any single logic function of up to 6 inputs, or any two logic functions requiring no more than 5 distinct inputs. The second LUT output has reduced speed, and therefore, must be used judiciously. We present techniques for dual-output LUT packing that lead to improved area-efficiency, with minimal performance degradation. We then describe packing techniques for large IP blocks, namely, block RAMs and DSPs. We pack circuits into the large blocks in a way that leverages the unique block RAM and DSP layout/architecture in Virtex-5, achieving significantly improved design performance.

References

[1]

Ahmed, T., Kundarewich, P., Anderson, J., Taylor, B., and Aggarwal, R. 2008. Architecture-specific packing for Virtex-5 FPGAs. In Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays. 5--13.

Digital Library

[2]

Altera. 2003. FLEX 10K Programmable Logic Device Datasheet. Altera Corp., San Jose, CA.

[3]

Betz, V. and Rose, J. 1997. Cluster-based logic blocks for FPGAs: Area-efficiency vs. input sharing and size. In Proceedings of the IEEE Custom Integrated Circuits Conference. 551--554.

[4]

Chen, D. and Cong, J. 2004. Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. In Proceedings of the ACM/IEEE International Symposium on Low-Power Electronics and Design. 70--73.

Digital Library

[5]

Dehkordi, M. and Brown, S. 2002. The effect of cluster packing and node duplication control in delay driven clustering. In Proceedings of the IEEE International Conference on Field-Programmable Technology. 227--233.

[6]

Eisenmann, H. and Johannes, F. 1998. Generic global placement and floor planning. In Proceedings of the ACM/IEEE Design Automation Conference. 269--274.

Digital Library

[7]

Gupta, S., Anderson, J., Farragher, L., and Wang, Q. 2007. CAD techniques for power optimization in Virtex-5 FPGAs. In Proceedings of the IEEE Custom Integrated Circuits Conference. 85--88.

[8]

Hassan, H., Anis, M., and Elmasry, M. 2005. Lap: A logic activity packing methodology for leakage power-tolerant FPGAs. In Proceedings of the ACM/IEEE International Symposium on Low-Power Electronics and Design. 257--262.

Digital Library

[9]

Hutton, M., Schleicher, J., Lewis, D., Pedersen, B., Yuan, R., Kaptanoglu, S., Baeckler, G., Ratchev, B., Padalia, K., and et. el. 2004. Improving FPGA performance and area using an adaptive logic module. In Proceedings of the International Conference on Field-Programmable Logic and Applications. 135--144.

[10]

Jang, S., Chan, B., Chung, K., and Mishchenko, A. 2008. Wiremap: FPGA technology mapping for improved routability. In Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays. 47--55.

Digital Library

[11]

Kuon, I. and Rose, J. 2007. Measuring the gap between FPGAs and ASICs. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 26, 2, 203--215.

Digital Library

[12]

Lamoureux, J. and Wilton, S. 2003. On the interaction between power-aware FPGA CAD algorithms. In Proceedings of the IEEE International Conference on Computer-Aided Design. 701--708.

Digital Library

[13]

Lin, J., Chen, D., and Cong, J. 2006. Optimal simultaneous mapping and clustering for FPGA delay optimization. In Proceedings of the ACM/IEEE Design Automation Conference. 472--477.

Digital Library

[14]

Marquardt, A., Betz, V., and Rose, J. 1999. Using cluster based logic blocks and timing-driven packing to improve FPGA speed and density. In Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays. 37--46.

Digital Library

[15]

Schabas, K. and Brown, S. 2003. Using logic duplication to improve performance in FPGAs. In Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays. 136--142.

Digital Library

[16]

Shang, L., Kaviani, A., and Bathala, K. 2002. Dynamic power consumption of the Virtex-2 FPGA family. In Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays. 157--164.

Digital Library

[17]

Singh, A. and Marek-Sadowska, M. 2002. Efficient circuit clustering for area and power reduction in FPGAs. In Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays. 59--66.

Digital Library

[18]

Viswanathan, N., Nam, G.-J., Alpert, C., Villarrubia, P., Ren, H., and Chu, C. 2007. RQL: Global placement via relaxed quadratic spreading and linearization. In Proceedings of the ACM/IEEE Design Automation Conference. 453--458.

Digital Library

[19]

Xilinx. 2007. Virtex-5 XtremeDSP Design Considerations User Guide. Xilinx Inc., San Jose, CA.

Cited By

Khadilkar SMargala M(2022)Optimizing open-source FPGA CAD tools2022 IEEE High Performance Extreme Computing Conference (HPEC)10.1109/HPEC55821.2022.9926347(1-4)Online publication date: 19-Sep-2022
https://doi.org/10.1109/HPEC55821.2022.9926347
Palchaudhuri ASharma SDhar A(2021)Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path InsertionACM Transactions on Design Automation of Electronic Systems10.1145/344620626:4(1-34)Online publication date: 22-Apr-2021
https://dl.acm.org/doi/10.1145/3446206
Petersen MNikolić SStojilović MShannon LAdler M(2021)NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAsThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439285(11-22)Online publication date: 17-Feb-2021
https://dl.acm.org/doi/10.1145/3431920.3439285
Show More Cited By

Index Terms

Packing Techniques for Virtex-5 FPGAs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

Recommendations

Architecture-specific packing for virtex-5 FPGAs
FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA -- the Xilinx Virtex-5 FPGA. Two aspects of packing are discussed: 1)packing for general logic ...
Clock power reduction for virtex-5 FPGAs
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx Virtex-5 FPGA are presented. The approaches are unique in that they leverage specific architectural ...
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
Special issue on application-specific processors

It is generally accepted that a custom hardware implementation of a set of computations will provide superior speed and energy efficiency relative to a software implementation. However, the cost and difficulty of hardware design is often prohibitive, ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 2, Issue 3

September 2009

121 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/1575774

Issue’s Table of Contents

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 2009

Accepted: 01 January 2009

Revised: 01 November 2008

Received: 01 June 2008

Published in TRETS Volume 2, Issue 3

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

14
Total Citations
View Citations
429
Total Downloads

Downloads (Last 12 months)23
Downloads (Last 6 weeks)0

Reflects downloads up to 22 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Khadilkar SMargala M(2022)Optimizing open-source FPGA CAD tools2022 IEEE High Performance Extreme Computing Conference (HPEC)10.1109/HPEC55821.2022.9926347(1-4)Online publication date: 19-Sep-2022
https://doi.org/10.1109/HPEC55821.2022.9926347
Palchaudhuri ASharma SDhar A(2021)Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path InsertionACM Transactions on Design Automation of Electronic Systems10.1145/344620626:4(1-34)Online publication date: 22-Apr-2021
https://dl.acm.org/doi/10.1145/3446206
Petersen MNikolić SStojilović MShannon LAdler M(2021)NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAsThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439285(11-22)Online publication date: 17-Feb-2021
https://dl.acm.org/doi/10.1145/3431920.3439285
Boutros ABetz V(2021)FPGA Architecture: Principles and ProgressionIEEE Circuits and Systems Magazine10.1109/MCAS.2021.307160721:2(4-29)Online publication date: Oct-2022
https://doi.org/10.1109/MCAS.2021.3071607
Khurshid BYousuf A(2020)Modifying FPGA Design Flow for Achieving better Circuit Optimizations2020 IEEE 17th India Council International Conference (INDICON)10.1109/INDICON49873.2020.9342221(1-5)Online publication date: 10-Dec-2020
https://doi.org/10.1109/INDICON49873.2020.9342221
Feng WGreene JMishchenko AAnderson JBazargan K(2018)Improving FPGA Performance with a S44 LUT StructureProceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3174243.3174272(61-66)Online publication date: 15-Feb-2018
https://dl.acm.org/doi/10.1145/3174243.3174272
Chen GPui CChow WLam KKuang JYoung EYu B(2018)RippleFPGAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.277805837:10(2022-2035)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2778058
Singhal LIyer MAdya S(2017)LSCProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062279(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062279
Palchaudhuri ADhar A(2017)Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs2017 IEEE 24th International Conference on High Performance Computing (HiPC)10.1109/HiPC.2017.00021(104-113)Online publication date: Dec-2017
https://doi.org/10.1109/HiPC.2017.00021
Parfieniuk MPark S(2016)On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAs2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2016.14(391-396)Online publication date: Jul-2016
https://doi.org/10.1109/ISVLSI.2016.14
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Issue’s Table of Contents