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Abstraction in Hardware System Design: Applying lessons from software languages to hardware languages using Bluespec SystemVerilog

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Rishiyur S. NikhilAuthors Info & Claims

Queue, Volume 9, Issue 8

Pages 40 - 54

https://doi.org/10.1145/2016036.2020861

Published: 18 August 2011 Publication History

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Abstract

The history of software engineering is one of continuing development of abstraction mechanisms designed to tackle ever-increasing complexity. Hardware design, however, is not as current. For example, the two most commonly used HDLs date back to the 1980s. Updates to the standards lag behind modern programming languages in structural abstractions such as types, encapsulation, and parameterization. Their behavioral semantics lag even further. They are specified in terms of event-driven simulators running on uniprocessor von Neumann machines.

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Cited By

Zacharopoulos GFerretti LGiaquinta EAnsaloni GPozzi L(2019)RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source CodeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281868938:4(741-754)Online publication date: Apr-2019
https://doi.org/10.1109/TCAD.2018.2818689
Harrison WGraves IProcter ABecchi MAllwein G(2016)A programming model for reconfigurable computing based in functional concurrency2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2016.7533911(1-8)Online publication date: Jun-2016
https://doi.org/10.1109/ReCoSoC.2016.7533911
Shao YBrooks D(2015)Research Infrastructures for Hardware AcceleratorsSynthesis Lectures on Computer Architecture10.2200/S00677ED1V01Y201511CAC03410:4(1-99)Online publication date: 18-Nov-2015
https://doi.org/10.2200/S00677ED1V01Y201511CAC034
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cover image Queue

Queue Volume 9, Issue 8

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August 2011

54 pages

ISSN:1542-7730

EISSN:1542-7749

DOI:10.1145/2016036

Issue’s Table of Contents

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 August 2011

Published in QUEUE Volume 9, Issue 8

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Cited By

Zacharopoulos GFerretti LGiaquinta EAnsaloni GPozzi L(2019)RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source CodeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281868938:4(741-754)Online publication date: Apr-2019
https://doi.org/10.1109/TCAD.2018.2818689
Harrison WGraves IProcter ABecchi MAllwein G(2016)A programming model for reconfigurable computing based in functional concurrency2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2016.7533911(1-8)Online publication date: Jun-2016
https://doi.org/10.1109/ReCoSoC.2016.7533911
Shao YBrooks D(2015)Research Infrastructures for Hardware AcceleratorsSynthesis Lectures on Computer Architecture10.2200/S00677ED1V01Y201511CAC03410:4(1-99)Online publication date: 18-Nov-2015
https://doi.org/10.2200/S00677ED1V01Y201511CAC034
Bacon DRabbah RShukla S(2013)FPGA Programming for the MassesQueue10.1145/2436696.244383611:2(40-52)Online publication date: 22-Feb-2013
https://dl.acm.org/doi/10.1145/2436696.2443836
Bacon DRabbah RShukla S(2013)FPGA programming for the massesCommunications of the ACM10.1145/2436256.243627156:4(56-63)Online publication date: 1-Apr-2013
https://dl.acm.org/doi/10.1145/2436256.2436271

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