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Power grid verification using node and branch dominance

Published: 05 June 2011 Publication History

Abstract

The verification of power grids in modern integrated circuits must start early in the design process when adjustments can be most easily incorporated. This work describes a vectorless verification technique that deals with circuit uncertainty in the framework of current constraints. In such a framework, grid verification becomes a question of computing the worst-case voltage drops which, in turn, entails the solution of as many linear programs (LPs) as there are nodes. First, we extend grid verification to also check for the worst-case branch currents. We show that this would require as many LPs as there are branches. Second, we propose a starkly different approach to reduce the number of LPs in the verification problem. We achieve this by examining dominance relations among node voltage drops and among branch currents. This allows us to replace a group of LPs by one conservative and tight LP. Results show a dramatic reduction in the number of LPs thus making vectorless grid verification in the framework of current constraints practical and scalable.

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I. A. Ferzli, F. N. Najm, and L. Kruze. A geometric approach for early power grid verification using current constraints. In ACM/IEEE ICCAD, pages 40--47, San Jose, CA, Nov. 5--8 2007.
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Cited By

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  • (2017)Fast Vectorless RLC Grid VerificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258989936:3(489-502)Online publication date: 1-Mar-2017
  • (2016)Generating Current Budgets to Guarantee Power Grid SafetyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.252465935:11(1914-1927)Online publication date: 1-Nov-2016
  • (2015)A Selected Inversion Approach for Locality Driven Vectorless Power Grid VerificationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.236552023:11(2617-2628)Online publication date: Nov-2015
  • Show More Cited By

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    cover image ACM Conferences
    DAC '11: Proceedings of the 48th Design Automation Conference
    June 2011
    1055 pages
    ISBN:9781450306362
    DOI:10.1145/2024724
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 05 June 2011

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    Author Tags

    1. dominance
    2. power grid
    3. voltage drop

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    View all
    • (2017)Fast Vectorless RLC Grid VerificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258989936:3(489-502)Online publication date: 1-Mar-2017
    • (2016)Generating Current Budgets to Guarantee Power Grid SafetyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.252465935:11(1914-1927)Online publication date: 1-Nov-2016
    • (2015)A Selected Inversion Approach for Locality Driven Vectorless Power Grid VerificationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.236552023:11(2617-2628)Online publication date: Nov-2015
    • (2015)Vectorless transient power grid verification: A case study with IBM benchmarks2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity10.1109/EMCSI.2015.7107698(271-276)Online publication date: Mar-2015
    • (2015)Generating circuit current constraints to guarantee power grid safetyThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059031(358-365)Online publication date: Jan-2015
    • (2014)Worst-Case Noise Area Prediction of On-Chip Power Distribution NetworkProceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop10.1145/2633948.2633950(1-8)Online publication date: 1-Jun-2014
    • (2013)Constraint abstraction for vectorless power grid verificationProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488841(1-6)Online publication date: 29-May-2013
    • (2013)Verifying RLC Power Grids With Transient Current ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.224803232:7(1059-1071)Online publication date: 1-Jul-2013
    • (2013)Selected inversion for vectorless power grid verification by exploiting locality2013 IEEE 31st International Conference on Computer Design (ICCD)10.1109/ICCD.2013.6657051(257-263)Online publication date: Oct-2013
    • (2012)Overview of vectorless/early power grid verificationProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429530(670-677)Online publication date: 5-Nov-2012

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