research-article

Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms

Authors:

Carlos Flores Fajardo,

German Fabila Garcia,

Li ZhaoAuthors Info & Claims

DAC '11: Proceedings of the 48th Design Automation Conference

Pages 966 - 971

https://doi.org/10.1145/2024724.2024938

Published: 05 June 2011 Publication History

Abstract

In an SoC, building local storage in each accelerator is area inefficient due to the low average utilization. In this paper, we present design and implementation of Buffer-integrated-Caching (BiC), which allows many buffers to be instantiated simultaneously in caches. BiC enables cores to view portions of the SRAM as cache while accelerators access other portions of the SRAM as private buffers.

We demonstrate the cost-effectiveness of BiC based on a recognition MPSoC that includes two Pentium^TM cores, an Augmented Reality accelerator and a speech recognition accelerator. With 3% extra area added to the baseline L2 cache, BiC eliminates the need to build 215KB dedicated SRAM for the accelerators, while increasing total cache misses by no more than 0.3%.

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Cited By

Krishna TKwon HParashar APellauer MSamajdar A(2020)Data Orchestration in Deep Learning AcceleratorsSynthesis Lectures on Computer Architecture10.2200/S01015ED1V01Y202005CAC05215:3(1-164)Online publication date: 17-Aug-2020
https://doi.org/10.2200/S01015ED1V01Y202005CAC052
Wittig RHasler MMatus EFettweis G(2019)Queue Based Memory Management Unit for Heterogeneous MPSoCs2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715129(1297-1300)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8715129
Pellauer MShao YClemons JCrago NHegde KVenkatesan RKeckler SFletcher CEmer JBahar IHerlihy MWitchel ELebeck A(2019)BuffetsProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304025(137-151)Online publication date: 4-Apr-2019
https://dl.acm.org/doi/10.1145/3297858.3304025
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Index Terms

Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Published In

cover image ACM Conferences

DAC '11: Proceedings of the 48th Design Automation Conference

June 2011

1055 pages

ISBN:9781450306362

DOI:10.1145/2024724

General Chair:
Leon Stok
IBM Corp., Hopewell Jct., NY
,
Program Chairs:
Nikil Dutt
Univ. of California, Irvine, CA
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2011

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DAC '11

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DAC '11: The 48th Annual Design Automation Conference 2011

June 5 - 10, 2011

California, San Diego

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Krishna TKwon HParashar APellauer MSamajdar A(2020)Data Orchestration in Deep Learning AcceleratorsSynthesis Lectures on Computer Architecture10.2200/S01015ED1V01Y202005CAC05215:3(1-164)Online publication date: 17-Aug-2020
https://doi.org/10.2200/S01015ED1V01Y202005CAC052
Wittig RHasler MMatus EFettweis G(2019)Queue Based Memory Management Unit for Heterogeneous MPSoCs2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715129(1297-1300)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8715129
Pellauer MShao YClemons JCrago NHegde KVenkatesan RKeckler SFletcher CEmer JBahar IHerlihy MWitchel ELebeck A(2019)BuffetsProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304025(137-151)Online publication date: 4-Apr-2019
https://dl.acm.org/doi/10.1145/3297858.3304025
Cong JFang ZHuang MWei PWu DYu C(2019)Customizable Computing—From Single Chip to DatacentersProceedings of the IEEE10.1109/JPROC.2018.2876372107:1(185-203)Online publication date: Jan-2019
https://doi.org/10.1109/JPROC.2018.2876372
Vijaykumar NJain AMajumdar DHsieh KPekhimenko GEbrahimi EHajinazar NGibbons PMutlu O(2018)A case for richer cross-layer abstractionsProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00027(207-220)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00027
Zhu YReddi V(2017)Optimizing General-Purpose CPUs for Energy-Efficient Mobile Web ComputingACM Transactions on Computer Systems10.1145/304102435:1(1-31)Online publication date: 20-Mar-2017
https://dl.acm.org/doi/10.1145/3041024
Shao YXi SSrinivasan VWei GBrooks DHsu WYang CLipasti MLee H(2016)Co-designing accelerators and SoC interfaces using gem5-aladdinThe 49th Annual IEEE/ACM International Symposium on Microarchitecture10.5555/3195638.3195697(1-12)Online publication date: 15-Oct-2016
https://dl.acm.org/doi/10.5555/3195638.3195697
Mantovani PCota EPilato CDi Guglielmo GCarloni L(2016)Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chipProceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.1145/2968455.2968509(1-10)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1145/2968455.2968509
Cota EMantovani PCarloni L(2016)Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator IntegrationProceedings of the 2016 International Conference on Supercomputing10.1145/2925426.2926258(1-12)Online publication date: 1-Jun-2016
https://dl.acm.org/doi/10.1145/2925426.2926258
Shao YXi SSrinivasan VWei GBrooks D(2016)Co-designing accelerators and SoC interfaces using gem5-Aladdin2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO.2016.7783751(1-12)Online publication date: Oct-2016
https://doi.org/10.1109/MICRO.2016.7783751
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