research-article

A design methodology to implement memory accesses in high-level synthesis

Authors:

Christian Pilato,

Fabrizio Ferrandi,

Donatella SciutoAuthors Info & Claims

CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 49 - 58

https://doi.org/10.1145/2039370.2039381

Published: 09 October 2011 Publication History

Abstract

Nowadays, the memory synthesis is becoming the main bottleneck for the generation of efficient hardware accelerators. This paper presents a design methodology to efficiently and automatically implement memory accesses in High-Level Synthesis. In particular, the approach starts from a behavioral specification (in pure C language) and a set of design constraints, such as the memory addresses where some of the data are stored.

The methodology classifies which variables can be internally or externally allocated to the different modules to generate the proper architecture, fully supporting a wide range of C constructs, such as pointer arithmetic, function calls and array accesses. Moreover it allows to parallelize the accesses when the memory address is known at compile time, resulting in an efficient execution of the specification.

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Cited By

Collini LTan BPilato CKarri RMitra TYoung EXiong J(2022)Reconfigurable Logic for Hardware IP ProtectionProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3561117(1-7)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3561117
Ramanathan NConstantinides GWickerson J(2022)A Case for Precise, Fine-Grained Pointer Synthesis in High-Level SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/349143027:4(1-26)Online publication date: 8-Mar-2022
https://dl.acm.org/doi/10.1145/3491430
Pilato CSoldavini S(2022)Accelerator Design with High-Level SynthesisHandbook of Computer Architecture10.1007/978-981-15-6401-7_19-1(1-33)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_19-1
Show More Cited By

Index Terms

A design methodology to implement memory accesses in high-level synthesis
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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cover image ACM Conferences

CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

October 2011

402 pages

ISBN:9781450307154

DOI:10.1145/2039370

Program Chairs:
Robert P. Dick
University of Michigan
,
Jan Madsen
Technical University of Denmark

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 October 2011

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ESWeek '11: Seventh Embedded Systems Week

October 9 - 14, 2011

Taipei, Taiwan

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Cited By

Collini LTan BPilato CKarri RMitra TYoung EXiong J(2022)Reconfigurable Logic for Hardware IP ProtectionProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3561117(1-7)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3561117
Ramanathan NConstantinides GWickerson J(2022)A Case for Precise, Fine-Grained Pointer Synthesis in High-Level SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/349143027:4(1-26)Online publication date: 8-Mar-2022
https://dl.acm.org/doi/10.1145/3491430
Pilato CSoldavini S(2022)Accelerator Design with High-Level SynthesisHandbook of Computer Architecture10.1007/978-981-15-6401-7_19-1(1-33)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_19-1
Pilato CWu KGarg SKarri RRegazzoni F(2018)TaintHLS: High-Level Synthesis For Dynamic Information Flow TrackingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.2834421(1-1)Online publication date: 2018
https://doi.org/10.1109/TCAD.2018.2834421
Pilato CGarg SWu KKarri RRegazzoni F(2018)Securing Hardware Accelerators: A New Challenge for High-Level SynthesisIEEE Embedded Systems Letters10.1109/LES.2017.277480010:3(77-80)Online publication date: Sep-2018
https://doi.org/10.1109/LES.2017.2774800
Kechiche LTouil LOuni B(2017)SOPC for real time multi-video treatments with QoS requirements2017 International Conference on Engineering & MIS (ICEMIS)10.1109/ICEMIS.2017.8273096(1-7)Online publication date: May-2017
https://doi.org/10.1109/ICEMIS.2017.8273096
Nane RSima VPilato CChoi JFort BCanis AChen YHsiao HBrown SFerrandi FAnderson JBertels K(2016)A Survey and Evaluation of FPGA High-Level Synthesis ToolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.251367335:10(1591-1604)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1109/TCAD.2015.2513673
Ravi SJoseph M(2016)Open source HLS tools: A stepping stone for modern electronic CAD2016 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)10.1109/ICCIC.2016.7919615(1-8)Online publication date: Dec-2016
https://doi.org/10.1109/ICCIC.2016.7919615
Fezzardi PFerrandi F(2016)Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers2016 26th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2016.7577369(1-9)Online publication date: Aug-2016
https://doi.org/10.1109/FPL.2016.7577369
Conti FPilkington CMarongiu ABenini L(2014)He-P2012: Architectural heterogeneity exploration on a scalable many-core platform2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2014.6868645(114-120)Online publication date: Jun-2014
https://doi.org/10.1109/ASAP.2014.6868645
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