research-article

SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs

Authors:

Andrea Marongiu,

Benjamin Lipton,

Maurice HerlihyAuthors Info & Claims

CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 39 - 48

https://doi.org/10.1145/2039370.2039380

Published: 09 October 2011 Publication History

Abstract

Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for transactional programming on embedded MPSoCs. Our proposal leverages a Hardware Transactional Memory (HTM) design, based on a dedicated HW module for conflict management, whose functionality is exposed to the software through compiler directives, implemented as an extension to the popular OpenMP programming model. To further improve ease of programming, our framework supports speculative parallelism, thanks to the ability of enforcing a given commit order in hardware. Our experimental results confirm that SoC-TM is a viable and cost-effective solution for embedded MPSoCs, in terms of energy, performance and productivity.

References

[1]

W. Baek, C. C. Minh, M. Trautmann, C. Kozyrakis, and K. Olukotun. The OpenTM transactional application programming interface. In PACT, pages 376--387, 2007.

Digital Library

[2]

B. H. Bloom. Space/time trade-offs in hash coding with allowable errors. Commun. ACM, 13:422--426, July 1970.

Digital Library

[3]

L. Ceze, J. Tuck, J. Torrellas, and C. Cascaval. Bulk disambiguation of speculative threads in multiprocessors. In ISCA, pages 227--238, 2006.

Digital Library

[4]

EEMBC. Eembc, the embedded microprocessor benchmark consortium. http://www.eembc.org.

[5]

C. Ferri, S. Wood, T. Moreshet, R. I. Bahar, and M. Herlihy. Embedded-tm: Energy and complexity-effective hardware transactional memory for embedded multicore systems. Journal of Parallel and Distributed Computing, 70(10):1042--1052, October 2010.

Digital Library

[6]

M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: A free, commercially representative embedded benchmark suite. In IEEE International Workshop on Workload Characterization, pages 3--14, 2001.

Digital Library

[7]

T. Harris, J. R. Larus, and R. Rajwar. Transactional memory, 2nd edition. Synthesis Lectures on Computer Architecture, 5(1):1--263, 2010.

Digital Library

[8]

A. Kejariwal, A. V. Veidenbaum, A. Nicolau, M. Girkar, X. Tian, and H. Saito. On the exploitation of loop-level parallelism in embedded applications. ACM Trans. Embed. Comput. Syst., 8:10:1--10:34, February 2009.

Digital Library

[9]

L. Kunz, G. Girão, and F. Wagner. Evaluation of a hardware transactional memory model in an NoC-based embedded MPSoC. In SBCCI, pages 85--90, São Paulo, Brazil, 2010.

Digital Library

[10]

F. Liu and V. Chaudhary. Extending OpenMP for heterogeneous chip multiprocessors. In International Conference on Parallel Processing, pages 161--168, 2003.

[11]

A. Marongiu and L. Benini. An OpenMP compiler for efficient use of distributed scratchpad memory in MPSoCs. Computers, IEEE Transactions on, PP(99):1, 2010.

Digital Library

[12]

M. Mehrara, J. Hao, P.-C. Hsu, and S. Mahlke. Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory. SIGPLAN Not., 44:166--176, June 2009.

Digital Library

[13]

Q. Meunier and F. Petrot. Lightweight transactional memory systems for nocs based architectures: Design, implementation and comparison of two policies. Journal of Parallel and Distributed Computing, 70(10):1024--1041, October 2010.

Digital Library

[14]

M. Milovanovic, R. Ferrer, O. Unsal, A. Cristal, X. Martorell, E. Ayguadé, J. Labarta, and M. Valero. Transactional memory and OpenMP. In B. Chapman, editor, A Practical Programming Model for the Multi-Core Era, pages 37--53. Springer Berlin/Heidelberg, 2008.

Digital Library

[15]

C. C. Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In International Symposium on Workload Characterization, Sept. 2008.

[16]

NVIDIA website. NVIDIA Tegra-2. http://www.nvidia.com/object/tegra-2.html.

[17]

K. O'Brien, K. O'Brien, Z. Sura, T. Chen, and T. Zhang. Supporting OpenMP on cell. In International Workshop on OpenMP, pages 65--76, 2008.

Digital Library

[18]

M. K. Prabhu and K. Olukotun. Exposing speculative thread parallelism in spec2000. In ACM Symposium on Principles and Practice of Parallel Programming, pages 142--152, 2005.

Digital Library

[19]

Qualcomm Inc. Snapdragon MSM8660 and APQ8060 Product Brief. http://www.qualcomm.com/documents/snapdragon-msm8x60-apq8060-product-brief.

[20]

R. Quislant, E. Gutierrez, O. Plata, and E. L. Zapata. Improving signatures by locality exploitation for transactional memory. In PACT, pages 303--312, 2009.

Digital Library

[21]

D. Sanchez, L. Yen, M. D. Hill, and K. Sankaralingam. Implementing signatures for transactional memory. In International Symposium on Microarchitecture, pages 123--133, 2007.

Digital Library

[22]

A. Shriraman, S. Dwarkadas, and M. L. Scott. Implementation tradeoffs in the design of flexible transactional memory support. Journal of Parallel and Distributed Computing, 70(10):1068--1084, October 2010.

Digital Library

[23]

C. von Praun, L. Ceze, and C. Caşcaval. Implicit parallelism with ordered transactions. In 12th symposium on Principles and practice of parallel programming, PPoPP '07, pages 79--89, New York, NY, USA, 2007. ACM.

Digital Library

[24]

L. Yen, J. Bobba, M. R. Marty, K. E. Moore, H. Volos, M. D. Hill, M. M. Swift, and D. A. Wood. LogTM-SE: Decoupling hardware transactional memory from caches. In HPCA, pages 261--272, 2007.

Digital Library

[25]

L. Yen, S. C. Draper, and M. D. Hill. Notary: Hardware techniques to enhance signatures. In International Symposium on Microarchitecture, pages 234--245, 2008.

Digital Library

[26]

H. Zhong, M. Mehrara, S. Lieberman, and S. Mahlke. Uncovering hidden loop level parallelism in sequential applications. In HPCA, pages 290--301, feb. 2008.

Cited By

Papagiannopoulou DMarongiu AMoreshet TBenini LHerlihy MBahar R(2018)Hardware Transactional Memory Exploration in Coherence-Free Many-Core ArchitecturesInternational Journal of Parallel Programming10.1007/s10766-018-0569-746:6(1304-1328)Online publication date: 1-Dec-2018
https://dl.acm.org/doi/10.1007/s10766-018-0569-7
Kottapalli VKhatri S(2016)A practical methodology to validate the statistical behavior of bloom filtersProceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.1145/2968456.2968461(1-8)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1145/2968456.2968461
Bortolotti DMarongiu ABenini L(2016)VirtualSoCACM Transactions on Embedded Computing Systems10.1145/293066516:1(1-27)Online publication date: 13-Oct-2016
https://dl.acm.org/doi/10.1145/2930665
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Index Terms

SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs

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Published In

cover image ACM Conferences

CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

October 2011

402 pages

ISBN:9781450307154

DOI:10.1145/2039370

Program Chairs:
Robert P. Dick
University of Michigan
,
Jan Madsen
Technical University of Denmark

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 October 2011

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ESWeek '11

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ESWeek '11: Seventh Embedded Systems Week

October 9 - 14, 2011

Taipei, Taiwan

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Papagiannopoulou DMarongiu AMoreshet TBenini LHerlihy MBahar R(2018)Hardware Transactional Memory Exploration in Coherence-Free Many-Core ArchitecturesInternational Journal of Parallel Programming10.1007/s10766-018-0569-746:6(1304-1328)Online publication date: 1-Dec-2018
https://dl.acm.org/doi/10.1007/s10766-018-0569-7
Kottapalli VKhatri S(2016)A practical methodology to validate the statistical behavior of bloom filtersProceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.1145/2968456.2968461(1-8)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1145/2968456.2968461
Bortolotti DMarongiu ABenini L(2016)VirtualSoCACM Transactions on Embedded Computing Systems10.1145/293066516:1(1-27)Online publication date: 13-Oct-2016
https://dl.acm.org/doi/10.1145/2930665
Aldea SEstebanez ALlanos DGonzalez-Escribano A(2016)An OpenMP Extension that Supports Thread-Level SpeculationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2015.239387027:1(78-91)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/TPDS.2015.2393870
Orosa LLourenco J(2016)A Hardware Approach to Detect, Expose and Tolerate High Level Data Races2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)10.1109/PDP.2016.57(159-167)Online publication date: Feb-2016
https://doi.org/10.1109/PDP.2016.57
Orosa LBruguera JAntelo E(2016)Asymmetric Allocation in a Shared Flexible Signature Module for Multicore ProcessorsThe Computer Journal10.1093/comjnl/bxw01059:10(1453-1469)Online publication date: 17-Mar-2016
https://doi.org/10.1093/comjnl/bxw010
Papagiannopoulou DMarongiu AMoreshet TBenini LHerlihy MBahar IJones ALi HCoskun AMargala M(2015)Playing with FireProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742090(9-14)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742090
Papagiannopoulou DCapodanno GMoreshet THerlihy MBahar R(2015)Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore SystemsACM Transactions on Embedded Computing Systems10.1145/270009714:3(1-27)Online publication date: 21-May-2015
https://dl.acm.org/doi/10.1145/2700097
Gonzalez-Mesa MGutierrez EZapata EPlata O(2014)Effective Transactional Memory Execution Management for Improved ConcurrencyACM Transactions on Architecture and Code Optimization10.1145/263304811:3(1-27)Online publication date: 13-Aug-2014
https://dl.acm.org/doi/10.1145/2633048
Papagiannopoulou DMoreshet TMarongiu ABenini LHerlihy MIris Bahar R(2014)Speculative synchronization for coherence-free embedded NUMA architectures2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)10.1109/SAMOS.2014.6893200(99-106)Online publication date: Jul-2014
https://doi.org/10.1109/SAMOS.2014.6893200
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