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Article

Notary: Hardware techniques to enhance signatures

Published: 08 November 2008 Publication History

Abstract

Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk, LogTM-SE, and SigTM). Signatures use fixed hardware to represent an unbounded number of addresses, but may lead to false conflicts (detecting a conflict when none exists). Previous work recommends that signatures be implemented with parallel Bloom filters with two or four hash functions (e.g., H3).

References

[1]
M. Abadi, A. Birrell, T. Harris, J. Hsieh, and M. Isard. Dynamic Separation for Transactional Memory. Tech. Report MSR-TR-2008- 43, Microsoft Research, 2008.
[2]
A. R. Alameldeen, C. J. Mauer, M. Xu, P. J. Harper, M. M. K. Martin, D. J. Sorin, M. D. Hill, and D. A. Wood. Evaluating Nondeterministic Multi-threaded Commercial Workloads. In Proc. of the 5th Workshop on Computer Architecture Evaluation Using Commercial Workloads, pages 30-38, Feb. 2002.
[3]
AMD Corporation. AMD Introduces the World's Most Advanced x86 Processor, Designed for the Demanding Datacenter. www.amd.com/usen/Corporate/VirtualPressRoom/0,51_104_543_15008~119768,00.html.
[4]
W. Baek, C. C. Minh, M. Trautmann, C. Kozyrakis, and K. Olukotun. The OpenTM Transactional Application Programming Interface. In PACT, Sept. 2007.
[5]
C. Ballapuram, K. Puttaswamy, G. H. Loh, and H.-H. S. Lee. Entropy-Based Low Power Data TLB Design. In Proc. of the Intnl. Conf. on Compilers, Architecture, and Synthesis for Embedded Systems, Oct. 2006.
[6]
J. C. Becker, A. Park, and M. Farrens. An Analysis of the Information Content of Address Reference Streams. In Micro-24, Nov. 1991.
[7]
B. H. Bloom. Space/Time Trade-offs in Hash Coding with Allowable Errors. Communications of the ACM, 13(7):422-426, July 1970.
[8]
J. L. Carter and M. N. Wegman. Universal Classes of Hash Functions (extended abstract). In Proceedings of the 9th Annual ACM Symposium on Theory of Computing, pages 106-112, 1977.
[9]
L. Ceze, J. Tuck, C. Cascaval, and J. Torrellas. Bulk Disambiguation of Speculative Threads in Multiprocessors. In ISCA-33, June 2006.
[10]
L. Ceze, J. Tuck, P. Montesinos, and J. Torrellas. BulkSC: Bulk Enforcement of Sequential Consistency. In ISCA-34, June 2007.
[11]
D. Citron and L. Rudolph. Creating a Wider Bus Using Caching Techniques. In HPCA-1, pages 90-99, Feb. 1995.
[12]
A. Gonzalez, M. Valero, N. Topham, and J. M. Parcerisa. Eliminating Cache Conflict Misses Through XOR-Based Placement Functions. In Proc. of the 1997 Intnl. Conf. on Supercomputing, July 1997.
[13]
D. W. Hammerstrom and E. S. Davidson. Information Content of CPU Memory Referencing Behavior. In ISCA-4, Mar. 1977.
[14]
M. Herlihy and J. E. B. Moss. Transactional Memory: Architectural Support for Lock-Free Data Structures. In ISCA-20, May 1993.
[15]
D. R. Hower and M. D. Hill. Rerun: Exploiting Episodes for Lightweight Race Recording. In ISCA-35, June 2008.
[16]
Internet Systems Consortium. Berkeley Internet Name Domain (BIND). http://www.isc.org/index.pl?/sw/bind/.
[17]
T. JINMEI and P. Vixie. Implementation and Evaluation of Moderate Parallelism in the BIND9 DNS Server. In 2006 USENIX Annual Technical Conference, June 2006.
[18]
M. Kharbutli, K. Irwin, Y. Solihin, and J. Lee. Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses. In HPCA-10, 2004.
[19]
M. Kharbutli, Y. Solihin, and J. Lee. Eliminating Conflict Misses Using Prime Number-Based Cache Indexing. IEEE TOC, 54(5), 2005.
[20]
P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-Way Multithreaded Sparc Processor. IEEE Micro, 25(2), Mar/Apr 2005.
[21]
J. R. Larus and R. Rajwar. Transactional Memory. Morgan & Claypool Publishers, 2007.
[22]
H. Le, W. Starke, J. Fields, F. O'Connell, D. Nguyen, B. Ronchetti, W. Sauer, E. Schwarz, and M. Vaden. IBM POWER6 microarchitecture. IBM Journal of R&D, 51(6), 2007.
[23]
B. Lucia, J. Devietti, K. Strauss, and L. Ceze. Atom-Aid: Detecting and Surviving Atomicity Violations. In ISCA-35, June 2008.
[24]
P. S. Magnusson et al. Simics: A Full System Simulation Platform. IEEE Computer, 35(2):50-58, Feb. 2002.
[25]
M. M. K. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood. Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset. Computer Architecture News, Sept. 2005.
[26]
A. Matveev, O. Shalev, and N. Shavit. Dynamic Identification of Shared Transactional Locations. Tech. report, Tel-Aviv Univ., 2007.
[27]
M. Milovanovic, R. Ferrer, O. S. Unsal, A. Cristal, X. Martorell, E. Ayguade, J. Labarta, and M. Valero. Transactional Memory and OpenMP. In Proceedings of the International Workshop on OpenMP, June 2007.
[28]
C. C. Minh, M. Trautmann, J. Chung, A. Mcdonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun. An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees. In ISCA-34, June 2007.
[29]
P. Montesinos, L. Ceze, and J. Torrellas. DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently. In ISCA-35, June 2008.
[30]
A. Park and M. Farrens. Address Compression Through Base Register Caching. In 23rd Annual Symposium and Workshop on Microprogramming and Microarchitectures, Nov. 1990.
[31]
M. Ramakrishna, E. Fu, and E. Bahcekapili. Efficient Hardware Hashing Functions for High Performance Computers. IEEE Transactions on Computers, 46(12):1378-1381, 1997.
[32]
B. R. Rau. Pseudo-randomly interleaved memory. In ISCA-18, 1991.
[33]
D. Sanchez, L. Yen, M. D. Hill, and K. Sankaralingam. Implementing Signatures for Transactional Memory. In Micro-40, Dec. 2007.
[34]
M. L. Scott, M. F. Spear, L. Dalessandro, and V. J. Marathe. Delaunay Triangulation with Transactions and Barriers. In IISWC, pages 107-113, Sept. 2007.
[35]
A. Seznec. A Case For Two-way Skewed-associative Caches. In ISCA-20, May 1993.
[36]
C. E. Shannon. Prediction and Entropy of Printed English. Bell Systems Technical Journal, (30):50-64, 1951.
[37]
M. F. Spear, V. J. Marathe, L. Dalessandro, and M. L. Scott. Privatization Techniques for Software Transactional Memory. Tech. Report 915, University of Rochester, Feb. 2007.
[38]
D. Tarjan, S. Thoziyoor, and N. P. Jouppi. CACTI 4.0. Technical Report HPL-2006-86, Hewlett Packard Labs, June 2006.
[39]
J. Tuck, W. Ahn, L. Ceze, and J. Torrellas. SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization. In ASPLOS-13, Mar. 2008.
[40]
H. Vandierendonck and K. D. Bosschere. XOR-Based Hash Functions. IEEE Transactions on Computers, 54(7):800-812, 2005.
[41]
J.-M. Wang, S.-C. Fang, and W.-S. Feng. New Efficient Designs for XOR and XNOR Functions on the Transistor Level. IEEE Journal of Solid-State Circuits, 29(7):780-786, 1994.
[42]
E. Witchel, J. Cates, and K. Asanovic. Mondrian memory protection. In ASPLOS-10, pages 304-316, Oct. 2002.
[43]
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In ISCA-22, pages 24-37, June 1995.
[44]
L. Yen. Signatures in Transactional Memory Systems. PhD thesis, University of Wisconsin, Expected Dec. 2008.
[45]
L. Yen, J. Bobba, M. R. Marty, K. E. Moore, H. Volos, M. D. Hill, M. M. Swift, and D. A. Wood. LogTM-SE: Decoupling Hardware Transactional Memory from Caches. In HPCA-13, Feb. 2007.
[46]
Z. Zhang, Z. Zhu, and X. Zhang. A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality. In Micro-33, Dec. 2000.

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cover image ACM Conferences
MICRO 41: Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
November 2008
483 pages
ISBN:9781424428366

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IEEE Computer Society

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Publication History

Published: 08 November 2008

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MICRO 41 Paper Acceptance Rate 40 of 210 submissions, 19%;
Overall Acceptance Rate 484 of 2,242 submissions, 22%

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  • (2019)Memory and Parallelism Analysis Using a Platform-Independent ApproachProceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems10.1145/3323439.3323988(23-26)Online publication date: 27-May-2019
  • (2018)Get out of the valleyProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00024(166-179)Online publication date: 2-Jun-2018
  • (2017)Leveraging irrevocability to deal with signature saturation in hardware transactional memoryThe Journal of Supercomputing10.1007/s11227-016-1944-z73:6(2525-2557)Online publication date: 1-Jun-2017
  • (2016)A practical methodology to validate the statistical behavior of bloom filtersProceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.1145/2968456.2968461(1-8)Online publication date: 1-Oct-2016
  • (2012)SnCTMProceedings of the 9th conference on Computing Frontiers10.1145/2212908.2212919(65-74)Online publication date: 15-May-2012
  • (2012)FlexSigACM Transactions on Architecture and Code Optimization10.1145/2086696.20867098:4(1-20)Online publication date: 26-Jan-2012
  • (2011)Unified locality-sensitive signatures for transactional memoryProceedings of the 17th international conference on Parallel processing - Volume Part I10.5555/2033345.2033379(326-337)Online publication date: 29-Aug-2011
  • (2011)SoC-TMProceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2039370.2039380(39-48)Online publication date: 9-Oct-2011
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  • (2011)Application-specific signatures for transactional memory in soft processorsACM Transactions on Reconfigurable Technology and Systems10.1145/2000832.20008334:3(1-14)Online publication date: 22-Aug-2011
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