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MFTL: A Design and Implementation for MLC Flash Memory Storage Systems

Published: 01 May 2012 Publication History
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  • Abstract

    NAND flash memory has gained its popularity in a variety of applications as a storage medium due to its low power consumption, nonvolatility, high performance, physical stability, and portability. In particular, Multi-Level Cell (MLC) flash memory, which provides a lower cost and higher density solution, has occupied the largest part of NAND flash-memory market share. However, MLC flash memory also introduces new challenges: (1) Pages in a block must be written sequentially. (2) Information to indicate a page being obsoleted cannot be recorded in its spare area due to the limitation on the number of partial programming. Since most of applications access NAND flash memory under FAT file system, this article designs an MLC Flash Translation Layer (MFTL) for flash-memory storage systems which takes constraints of MLC flash memory and access behaviors of FAT file system into consideration. A series of trace-driven simulations was conducted to evaluate the performance of the proposed scheme. Although MFTL is designed for MLC flash memory and FAT file system, it is applicable to SLC flash memory and other file systems as well. Our experiment results show that the proposed MFTL could achieve a good performance for various access patterns even on SLC flash memory.

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    Cited By

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    • (2018)Data pattern aware FTL for SLC+MLC hybrid SSDDesign Automation for Embedded Systems10.1007/s10617-014-9138-519:1-2(101-127)Online publication date: 20-Dec-2018
    • (2016)A Cache-Based Flash Translation Layer for TLC-Based Multimedia Storage DevicesACM Transactions on Embedded Computing Systems (TECS)10.1145/282061415:1(1-28)Online publication date: 13-Jan-2016
    • (2014)Fast responsive flash translation layer for smart devicesIEEE Transactions on Consumer Electronics10.1109/TCE.2014.678092560:1(52-59)Online publication date: Feb-2014
    • Show More Cited By

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    Published In

    cover image ACM Transactions on Storage
    ACM Transactions on Storage  Volume 8, Issue 2
    May 2012
    89 pages
    ISSN:1553-3077
    EISSN:1553-3093
    DOI:10.1145/2180905
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 01 May 2012
    Accepted: 01 December 2011
    Revised: 01 October 2011
    Received: 01 May 2011
    Published in TOS Volume 8, Issue 2

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    Author Tags

    1. FAT file system
    2. Multi-level cell flash memory
    3. storage management

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    Cited By

    View all
    • (2018)Data pattern aware FTL for SLC+MLC hybrid SSDDesign Automation for Embedded Systems10.1007/s10617-014-9138-519:1-2(101-127)Online publication date: 20-Dec-2018
    • (2016)A Cache-Based Flash Translation Layer for TLC-Based Multimedia Storage DevicesACM Transactions on Embedded Computing Systems (TECS)10.1145/282061415:1(1-28)Online publication date: 13-Jan-2016
    • (2014)Fast responsive flash translation layer for smart devicesIEEE Transactions on Consumer Electronics10.1109/TCE.2014.678092560:1(52-59)Online publication date: Feb-2014
    • (2013)VASTIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.225058232:8(1137-1150)Online publication date: 1-Aug-2013

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