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Embra: fast and flexible machine simulation

Published: 15 May 1996 Publication History

Abstract

This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simulation environment, Embra models the processors of a MIPS R3000/R4000 machine faithfully enough to run a commercial operating system and arbitrary user applications. To achieve high simulation speed, Embra uses dynamic binary translation to generate code sequences which simulate the workload. It is the first machine simulator to use this technique. Embra can simulate real workloads such as multiprocess compiles and the SPEC92 benchmarks running on Silicon Graphic's IRIX 5.3 at speeds only 3 to 9 times slower than native execution of the workload, making Embra the fastest reported complete machine simulator. Dynamic binary translation also gives Embra the flexibility to dynamically control both the simulation statistics reported and the simulation model accuracy with low performance overheads. For example, Embra can customize its generated code to include a processor cache model which allows it to compute the cache misses and memory stall time of a workload. Customized code generation allows Embra to simulate a machine with caches at slowdowns of only a factor of 7 to 20. Most of the statistics generated at this speed match those produced by a slower reference simulator to within 1%. This paper describes the techniques used by Embra to achieve high performance, focusing on the requirements unique to machine simulation, including modeling the processor, memory management unit, and caches. In order to study Embra's memory system performance we use the SimOS simulation system to examine Embra itself. We present a detailed breakdown of Embra's memory system performance for two cache hierarchies to understand Embra's current performance and to show that Embra's implementation techniques benefit significantly from the larger cache hierarchies that are becoming available. Embra has been used for operating system development and testing as well as for studies of computer architecture. In this capacity it has simulated large, commercial workloads including IRIX running a relational database system and a CAD system for billions of simulated machine cycles.

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Published In

cover image ACM SIGMETRICS Performance Evaluation Review
ACM SIGMETRICS Performance Evaluation Review  Volume 24, Issue 1
May 1996
273 pages
ISSN:0163-5999
DOI:10.1145/233008
Issue’s Table of Contents
  • cover image ACM Conferences
    SIGMETRICS '96: Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
    May 1996
    279 pages
    ISBN:0897917936
    DOI:10.1145/233013
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 May 1996
Published in SIGMETRICS Volume 24, Issue 1

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  • (2017)Dynamic Binary Translation of VLIW Codes on Scalar ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.260429436:5(789-800)Online publication date: 1-May-2017
  • (2017)Optimizing Memory Access Performance Using Hardware Assisted Virtualization in Retargetable Dynamic Binary Translation2017 Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2017.41(40-46)Online publication date: Aug-2017
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  • (2017)Multi-Processor System-on-Chip Prototyping Using Dynamic Binary TranslationHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_20-1(1-27)Online publication date: 10-Apr-2017
  • (2017)Multiprocessor System-on-Chip Prototyping Using Dynamic Binary TranslationHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_20(565-591)Online publication date: 27-Sep-2017
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