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A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture

Published: 07 October 2012 Publication History

Abstract

In this paper, we propose a flexible NoC architecture and a dynamic distributed routing algorithm which can enhance the NoC communication performance with minimal energy overhead. In particular, our proposed NoC architecture exploits the following two features: i) self-reconfigurable bidirectional channels to increase the effective bandwidth and ii) express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at run time in the network. A deadlock-free and traffic-aware dynamic routing algorithm is further developed for the proposed architecture, which can take advantage of the increased flexibility in the proposed architecture. Both the channels self-reconfiguration and routing decisions are made in a distributed fashion, based on a function of the localized traffic conditions, in order to maximize the performance and minimize the energy costs at the macroscopic level. Our simulation results show that the proposed approach can reduce the network latency by 30\% -80\% in most cases compared to a conventional unidirectional mesh topology, while incurring less than 15\% power overhead.

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Cited By

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  • (2024)Efficient Topology Reconfiguration for NoC-Based Multiprocessors: A Greedy-Memetic AlgorithmJournal of Parallel and Distributed Computing10.1016/j.jpdc.2024.104904(104904)Online publication date: Apr-2024
  • (2021)ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore ArchitecturesIEEE Transactions on Sustainable Computing10.1109/TSUSC.2020.29813406:2(274-288)Online publication date: 1-Apr-2021
  • (2021)A Voting Approach for Adaptive Network-on-Chip Power-GatingIEEE Transactions on Computers10.1109/TC.2020.303316370:11(1962-1975)Online publication date: 1-Nov-2021
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  1. A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture

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    cover image ACM Conferences
    CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
    October 2012
    596 pages
    ISBN:9781450314268
    DOI:10.1145/2380445
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 07 October 2012

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    Author Tags

    1. adaptive routing
    2. bidirectional link
    3. congestion control
    4. fitness based routing
    5. network-on-chip
    6. traffic characteristics

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    ESWEEK'12
    ESWEEK'12: Eighth Embedded System Week
    October 7 - 12, 2012
    Tampere, Finland

    Acceptance Rates

    CODES+ISSS '12 Paper Acceptance Rate 48 of 163 submissions, 29%;
    Overall Acceptance Rate 280 of 864 submissions, 32%

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    ESWEEK '24
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    Cited By

    View all
    • (2024)Efficient Topology Reconfiguration for NoC-Based Multiprocessors: A Greedy-Memetic AlgorithmJournal of Parallel and Distributed Computing10.1016/j.jpdc.2024.104904(104904)Online publication date: Apr-2024
    • (2021)ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore ArchitecturesIEEE Transactions on Sustainable Computing10.1109/TSUSC.2020.29813406:2(274-288)Online publication date: 1-Apr-2021
    • (2021)A Voting Approach for Adaptive Network-on-Chip Power-GatingIEEE Transactions on Computers10.1109/TC.2020.303316370:11(1962-1975)Online publication date: 1-Nov-2021
    • (2020)An Enhanced Dynamic Weighted Incremental Technique for QoS Support in NoCACM Transactions on Parallel Computing10.1145/33914427:2(1-31)Online publication date: 18-May-2020
    • (2020)Addressing a New Class of Reliability Threats in 3-D Network-on-ChipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.291784639:7(1358-1371)Online publication date: 17-Jun-2020
    • (2020)Advance Virtual Channel ReservationIEEE Transactions on Computers10.1109/TC.2020.297198269:9(1320-1334)Online publication date: 1-Sep-2020
    • (2020)TAGO: Rethinking Routing Design in High Performance Reconfigurable NetworksSC20: International Conference for High Performance Computing, Networking, Storage and Analysis10.1109/SC41405.2020.00029(1-16)Online publication date: Nov-2020
    • (2020)Off-Chip Congestion Management for GPU-based Non-Uniform Processing-in-Memory Networks2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/PDP50117.2020.00050(282-289)Online publication date: Mar-2020
    • (2020) NoC 2 : An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems IEEE Access10.1109/ACCESS.2020.30306068(185992-186011)Online publication date: 2020
    • (2019)BARANACM Transactions on Parallel Computing10.1145/32940495:3(1-29)Online publication date: 22-Jan-2019
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