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Functional verification methodology for the PowerPC 604 microprocessor

Authors:

James Monaco,

David Holloway,

Rajesh RainaAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 319 - 324

https://doi.org/10.1145/240518.240579

Published: 01 June 1996 Publication History

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References

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"The 68060 Microprocessor Functional Design and Verification Methodology", J. Freeman, R. Duerden, M. Miller, and C. Taylor, Proceedings of the Design SuperCon '95 On-Chip Design Conference, March 1995, Santa Clara, CA.

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"PowerPCTM 604: RISC Microprocessor User's Manual", Technical Document, Motorola Order Number MPC604UM/AD, 1994.

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"Test Program Generation for Functional Verification of PowerPC Processors in IBM", A. Aharon et. al.; pp. 279-285, Proceedings of the 32nd Design Automation Conference, June 1995, San Francisco, CA.

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"An Automatic Simulation Environment for PowerPCTM Design Verification", J. Monaco and J. Kasha, Proceedings of the Design SuperCon'95 On-Chip Design Conference, March 1995, Santa Clara, CA.

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"Functional Coverage Assessment for PowerPCTM Microprocessors and Chipsets", D. McKinney, B. Plessier, and J. Monaco, Proceedings of the Design SuperCon '96 On-Chip Design Conference, February 1996, Santa Clara, CA.

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Cited By

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Wang HLiu SZhang L(2022)A 32-Bit DSP Instruction Pipeline Control Unit Verification Method Based on Instruction Reordering StrategySymmetry10.3390/sym1404064614:4(646)Online publication date: 22-Mar-2022
https://doi.org/10.3390/sym14040646
Sadasivam SAlapati SMallikarjunan V(2012)Test Generation Approach for Post-Silicon Validation of High End MicroprocessorProceedings of the 2012 15th Euromicro Conference on Digital System Design10.1109/DSD.2012.148(830-836)Online publication date: 5-Sep-2012
https://dl.acm.org/doi/10.1109/DSD.2012.148
Sung WOu SLiu YChen C(2012)Employed VeriLite simulation to improve SOC design and verificationComputer Applications in Engineering Education10.1002/cae.2040420:2(374-382)Online publication date: 11-Apr-2012
https://doi.org/10.1002/cae.20404
Show More Cited By

Index Terms

Functional verification methodology for the PowerPC 604 microprocessor
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
      1. Microcomputers
2. Hardware
  1. Hardware validation
    1. Functional verification

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The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor
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This paper presents the use of formal methods in the design of a PowerPC microprocessor. The chosen methodology employs two independently developed design views, a register-transfer level specification for efficient system simulation and a transistor ...
Design of the PowerPC 604e microprocessor
COMPCON '96: Proceedings of the 41st IEEE International Computer Conference

The PowerPC 604e microprocessor is a lower power, higher performance extension of the PowerPC 604 microprocessor. The 604e doubles the cache size and times the performance of memory accesses compared to the original 604. The 604e has also added hardware ...

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Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

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DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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View all

Wang HLiu SZhang L(2022)A 32-Bit DSP Instruction Pipeline Control Unit Verification Method Based on Instruction Reordering StrategySymmetry10.3390/sym1404064614:4(646)Online publication date: 22-Mar-2022
https://doi.org/10.3390/sym14040646
Sadasivam SAlapati SMallikarjunan V(2012)Test Generation Approach for Post-Silicon Validation of High End MicroprocessorProceedings of the 2012 15th Euromicro Conference on Digital System Design10.1109/DSD.2012.148(830-836)Online publication date: 5-Sep-2012
https://dl.acm.org/doi/10.1109/DSD.2012.148
Sung WOu SLiu YChen C(2012)Employed VeriLite simulation to improve SOC design and verificationComputer Applications in Engineering Education10.1002/cae.2040420:2(374-382)Online publication date: 11-Apr-2012
https://doi.org/10.1002/cae.20404
Wen CWang LBhadra JGielen G(2007)An incremental learning framework for estimating signal controllability in unit-level verificationProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326126(250-257)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326126
Verma SHarris IRamineni KLauwereins RMadsen J(2007)Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptionsProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266560(900-905)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266560
Silveira Gda Silva KMelcher EPetraglia APedroni VCauwenberghs G(2007)Functional verification of an MPEG-4 decoder design using a random constrained movie generatorProceedings of the 20th annual conference on Integrated circuits and systems design10.1145/1284480.1284573(360-364)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.1145/1284480.1284573
Yang FHuang WHuang ILevitan S(2007)Automatic verification of external interrupt behaviors for microprocessor designProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278701(896-901)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278701
Vardi MLevitan S(2007)Formal techniques for SystemC verificationProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278527(188-192)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278527
Nakamura Y(2006)Software Verification for System on a Chip using a C/C++ Simulator and FPGA Emulator2006 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2006.258142(1-4)Online publication date: Dec-2006
https://doi.org/10.1109/VDAT.2006.258142
Nakamura YHosokawa KKuroda IYoshikawa KYoshimura TMalik SFix LKahng A(2004)A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communicationProceedings of the 41st annual Design Automation Conference10.1145/996566.996655(299-304)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996655
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The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor

Formal verification of a PowerPC microprocessor

Design of the PowerPC 604e microprocessor

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The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor

Formal verification of a PowerPC microprocessor

Design of the PowerPC 604e microprocessor

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