Browse Books

Reviewer: Harry Frederick Jordan

As a manual for a family of processors, this book faces problems in exposition worse than those encountered in an ordinary computer manual. Any attempt to explain features in terms of underlying mechanisms is stalled by the desire to leave implementation details open to designers of future members of the family. Thus the reader should not expect insight into the rationale of the architecture but, as the title says, a specification. Coherence is further reduced by the separation of the specification into three “books.” Book 1 specifies the instruction set as seen by a non-privileged user programming for a flat address space without cache or virtual memory. Book 2 extends the specification to cache, shared storage, and timer. The treatment is still at the non-privileged level and specifies only instructions such as cache block invalidate and flush and timer reads, which can be executed by the applications programmer. Book 3 treats the architecture of the operating environment, specifying instructions whose execution is privileged. The discussion of virtual storage is contained in this book, as is the treatment of interrupts. The introduction notes the need for a Book 4 for each distinct implementation of the architecture. Little is said about the expected content of Book 4. The advantage of subject partitioning inherent in the division into three books is offset by the fact that the circular dependences present in any machine manual now travel between books. For example, a good overview of the total memory hierarchy is hard to get because the treatments of cache and virtual memory appear in different books. Because it is a joint project of several companies, the Power PC promises to have an important impact. While including many concepts developed in connection with RISC processors, the architecture specifies a rather complex instruction set computer. The number of variants of individual instructions is also large. The desire to be all things to all people is typified by not only having big-endian and little-endian operating modes but also including byte-reversed loads and stores. Initial compilers supplied with early systems employing the architecture will probably use only a narrow range of the possibilities offered by the instruction set. It will be interesting to see what measurements of instruction set usage over the life of the machine reveal about instruction use frequency. This book is very much a computer family specification manual. There is no hint of textbook about it. The index, the only one for the three books, is brief. For example, neither input, output, nor I/O appears, so it is hard to discover that I/O is considered to be strictly a part of the memory system. Like any other manual, this book should be used as a reference work, though finding the appropriate material may take some effort.