research-article

Local merges for effective redundancy in clock networks

Authors:

Cheng-Kok KohAuthors Info & Claims

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

Pages 162 - 167

https://doi.org/10.1145/2451916.2451957

Published: 24 March 2013 Publication History

Abstract

Process and environmental variations affect the reliability of clock networks. By synthesizing non-tree structures, the robustness of clock networks can be improved at the expense of higher capacitance. A cheap way of converting a tree structure to a non-tree structure is to insert cross links. Unfortunately, the robustness seems to improve only when the links are sufficiently short. Other non-tree structures such as meshes and multilevel fusion trees improve the robustness more effectively, but with much higher cost. In this work, we develop a new non-tree topology by merging a sub-clock tree with all other sub-clock trees that contain sequential elements that require strict synchronization. Results show that when compared with the state-of-the-art solutions, clock networks constructed with the proposed structure have similar capacitance but notable improved robustness. moreover, the clock networks can satisfy tight skew constraints even when simulated under a more stringent variations model, with 22% lower capacitance when compared to solutions in earlier studies.

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Cited By

Farshidi ARakai LBehjat LWestwick D(2016)Variation-aware clock network buffer sizing using robust multi-objective optimizationOptimization and Engineering10.1007/s11081-016-9317-217:2(473-500)Online publication date: 1-Apr-2016
https://doi.org/10.1007/s11081-016-9317-2
Roy SPan DMattheakis PColyer PMasse-Navette LRibet PJones ALi HCoskun AMargala M(2015)Skew Bounded Buffer Tree Resynthesis For Clock Power OptimizationProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742119(87-90)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742119
Rakai LFarshidi AWestwick DBehjat L(2014)Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing ProblemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.229306733:4(532-545)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1109/TCAD.2013.2293067
Show More Cited By

Index Terms

Local merges for effective redundancy in clock networks
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

March 2013

194 pages

ISBN:9781450319546

DOI:10.1145/2451916

General Chair:
Cheng-Kok Koh
Purdue University
,
Program Chair:
Cliff Sze
IBM Research

Copyright © 2013 ACM.

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Published: 24 March 2013

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March 24 - 27, 2013

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Cited By

Farshidi ARakai LBehjat LWestwick D(2016)Variation-aware clock network buffer sizing using robust multi-objective optimizationOptimization and Engineering10.1007/s11081-016-9317-217:2(473-500)Online publication date: 1-Apr-2016
https://doi.org/10.1007/s11081-016-9317-2
Roy SPan DMattheakis PColyer PMasse-Navette LRibet PJones ALi HCoskun AMargala M(2015)Skew Bounded Buffer Tree Resynthesis For Clock Power OptimizationProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742119(87-90)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742119
Rakai LFarshidi AWestwick DBehjat L(2014)Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing ProblemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.229306733:4(532-545)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1109/TCAD.2013.2293067
Farshidi ARakai LBehjat LWestwick D(2014)Optimal gate sizing using a self-tuning multi-objective frameworkIntegration10.1016/j.vlsi.2013.10.00847:3(347-355)Online publication date: Jun-2014
https://doi.org/10.1016/j.vlsi.2013.10.008

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