research-article

Tri-level-cell phase change memory: toward an efficient and reliable memory system

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Hsien-Hsin S. LeeAuthors Info & Claims

ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture

Pages 440 - 451

https://doi.org/10.1145/2485922.2485960

Published: 23 June 2013 Publication History

Abstract

There are several emerging memory technologies looming on the horizon to compensate the physical scaling challenges of DRAM. Phase change memory (PCM) is one such candidate proposed for being part of the main memory in computing systems. One salient feature of PCM is its multi-level-cell (MLC) property, which can be used to multiply the memory capacity at the cell level. However, due to the nature of PCM that the value written to the cell can drift over time, PCM is prone to a unique type of soft errors, posing a great challenge for their practical deployment. This paper first quantitatively studied the current art for MLC PCM in dealing with the resistance drift problem and showed that the previously proposed techniques such as scrubbing or error correction mechanisms have significant reliability challenges to overcome. We then propose tri-level-cell PCM and demonstrate its ability to achieving 10⁵ x lower soft error rate than four-level-cell PCM and 1.33 x higher information density than single-level-cell PCM. According to our findings, the tri-level-cell PCM shows 36.4% performance improvement over the four-level-cell PCM while achieving the soft error rate of DRAM.

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Nguyen TImran MChoi JYang J(2024)HYDRA: A Hybrid Resistance Drift Resilient Architecture for Phase Change Memory-Based Neural Network AcceleratorsIEEE Transactions on Computers10.1109/TC.2024.340409673:9(2123-2135)Online publication date: Sep-2024
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ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture

June 2013

686 pages

ISBN:9781450320795

DOI:10.1145/2485922

General Chair:
Avi Mendelson
Technion

ACM SIGARCH Computer Architecture News Volume 41, Issue 3
ICSA '13
June 2013
666 pages
ISSN:0163-5964
DOI:10.1145/2508148
Issue’s Table of Contents

Copyright © 2013 ACM.

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Published: 23 June 2013

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ISCA'13: The 40th Annual International Symposium on Computer Architecture

June 23 - 27, 2013

Tel-Aviv, Israel

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ISCA '13 Paper Acceptance Rate 56 of 288 submissions, 19%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

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https://doi.org/10.23919/DATE58400.2024.10546752
Nguyen TImran MChoi JYang J(2024)HYDRA: A Hybrid Resistance Drift Resilient Architecture for Phase Change Memory-Based Neural Network AcceleratorsIEEE Transactions on Computers10.1109/TC.2024.340409673:9(2123-2135)Online publication date: Sep-2024
https://doi.org/10.1109/TC.2024.3404096
Wu RShen ZYang ZShu J(2024)Mitigating Write Disturbance in Non-Volatile Memory via Coupling Machine Learning with Out-of-Place Updates2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00092(1184-1198)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00092
Zhang QLian CXu QYu YSkowronski M(2023)Density of amorphous sputtered Ge2Sb2Te5 thin filmsAIP Advances10.1063/5.013347713:1Online publication date: 13-Jan-2023
https://doi.org/10.1063/5.0133477
Nguyen TImran MYang JMitra TYoung EXiong J(2022)DynaPATProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549400(1-9)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3549400
Imran MKwon TYang J(2022)ADAPT: A Write Disturbance-Aware Programming Technique for Scaled Phase Change MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.306870441:4(950-963)Online publication date: Apr-2022
https://doi.org/10.1109/TCAD.2021.3068704
Imran MKwon TTouba NYang J(2022)CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCMIEEE Transactions on Computers10.1109/TC.2021.306857771:5(992-1007)Online publication date: 1-May-2022
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Kwon TImran MYang J(2021)Reliability Enhanced Heterogeneous Phase Change Memory Architecture for Performance and Energy EfficiencyIEEE Transactions on Computers10.1109/TC.2020.300949870:9(1388-1400)Online publication date: 1-Sep-2021
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Zhang YYu ZGu LWang CFeng D(2021)EnTiered-ReRAM: An Enhanced Low Latency and Energy Efficient TLC Crossbar ReRAM ArchitectureIEEE Access10.1109/ACCESS.2021.31298789(167173-167189)Online publication date: 2021
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Hong JLee YKim YHan T(2020)Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change MemoryElectronics10.3390/electronics90406269:4(626)Online publication date: 9-Apr-2020
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