research-article

Quality of service capabilities for hard real-time applications on multi-core processors

Authors:

Michael PaulitschAuthors Info & Claims

RTNS '13: Proceedings of the 21st International conference on Real-Time Networks and Systems

Pages 151 - 160

https://doi.org/10.1145/2516821.2516826

Published: 16 October 2013 Publication History

Abstract

Computing Worst-Case Execution Times (WCETs) for applications executed on multi-core processors is a challenging topic since possible interferences on shared resources need to be considered. Some approaches are already proposed in literature, but the problem is still not sufficiently solved. Different approaches suffer different shortcomings. For instance, the mutual analysis of multiple applications leads to great computational complexity, pessimistic assumptions on the interference between tasks causes highly overestimated WCETs and resource privatisation dissipates processor resources. In this paper we tackle the problems of overestimated WCETs due to pessimistic analysis and differences between average-case and worst-case execution timing. We introduce a new computing paradigm for safety-critical real-time systems, which enables Quality of Service (QoS) properties to increase the utilisation of multi-core processors while still guaranteeing bounds on the worst-case behavior. This paradigm is one approach to raise multi-core performance over single-core processors, even for hard real-time systems. For evaluation we use abstractions of real applications. The concepts are implemented on Freescale's P4080 multi-core processor and AbsInt's timing analysis framework aiT. The results show an increased processor core and system utilisation of up to 99.9% and 59.3% respectively, while still providing hard deadline guarantees for all applications.

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Farina GGala GCinque MFohler G(2023)Enabling memory access isolation in real-time cloud systems using Intel’s detection/regulation capabilitiesJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2023.102848137:COnline publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1016/j.sysarc.2023.102848
Farina GGala GCinque MFohler G(2022)Assessing Intel’s Memory Bandwidth Allocation for resource limitation in real-time systems2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC)10.1109/ISORC52572.2022.9812757(1-8)Online publication date: 17-May-2022
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Zini MCicero GCasini DBiondi A(2021)Profiling and controlling I/O‐related memory contention in COTS heterogeneous platformsSoftware: Practice and Experience10.1002/spe.305352:5(1095-1113)Online publication date: 10-Nov-2021
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cover image ACM Other conferences

RTNS '13: Proceedings of the 21st International conference on Real-Time Networks and Systems

October 2013

298 pages

ISBN:9781450320580

DOI:10.1145/2516821

General Chairs:
Michel Auguin
LEAT, Nice, France
,
Robert de Simone
INRIA, Sophia Antipolis, France
,
Program Chairs:
Robert Davis
University of York, UK
,
Emmanuel Grolleau
LIAS, ISAE-ENSMA, France

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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CNRS: Centre National De La Rechercue Scientifique
INRIA: Institut Natl de Recherche en Info et en Automatique

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Association for Computing Machinery

New York, NY, United States

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Published: 16 October 2013

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RTNS 2013

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INRIA

RTNS 2013: 21st International Conference on Real-Time Networks and Systems

October 16 - 18, 2013

Sophia Antipolis, France

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RTNS '13 Paper Acceptance Rate 29 of 62 submissions, 47%;

Overall Acceptance Rate 119 of 255 submissions, 47%

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Cited By

Farina GGala GCinque MFohler G(2023)Enabling memory access isolation in real-time cloud systems using Intel’s detection/regulation capabilitiesJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2023.102848137:COnline publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1016/j.sysarc.2023.102848
Farina GGala GCinque MFohler G(2022)Assessing Intel’s Memory Bandwidth Allocation for resource limitation in real-time systems2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC)10.1109/ISORC52572.2022.9812757(1-8)Online publication date: 17-May-2022
https://doi.org/10.1109/ISORC52572.2022.9812757
Zini MCicero GCasini DBiondi A(2021)Profiling and controlling I/O‐related memory contention in COTS heterogeneous platformsSoftware: Practice and Experience10.1002/spe.305352:5(1095-1113)Online publication date: 10-Nov-2021
https://doi.org/10.1002/spe.3053
Maiza CRihani HRivas JGoossens JAltmeyer SDavis R(2019)A Survey of Timing Verification Techniques for Multi-Core Real-Time SystemsACM Computing Surveys10.1145/332321252:3(1-38)Online publication date: 18-Jun-2019
https://dl.acm.org/doi/10.1145/3323212
Skalistis SKritikakou A(2019)Timely Fine-Grained Interference-Sensitive Run-Time Adaptation of Time-Triggered Schedules2019 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS46320.2019.00030(233-245)Online publication date: Dec-2019
https://doi.org/10.1109/RTSS46320.2019.00030
Agrawal AMancuso RPellizzoni RFohler G(2018)Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems2018 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS.2018.00040(230-241)Online publication date: Dec-2018
https://doi.org/10.1109/RTSS.2018.00040
Agrawal AFohler GJacob B(2017)DRAM-related challenges in task scheduling with timing predictability on COTS multi-cores for safety-critical systemsProceedings of the International Symposium on Memory Systems10.1145/3132402.3132417(265-267)Online publication date: 2-Oct-2017
https://dl.acm.org/doi/10.1145/3132402.3132417
Kritikakou AMarty TRoy M(2017)DYNASCOREACM Transactions on Design Automation of Electronic Systems10.1145/311022223:2(1-26)Online publication date: 5-Oct-2017
https://dl.acm.org/doi/10.1145/3110222
Yun HAli WGondi SBiswas S(2017)BWLOCK: A Dynamic Memory Access Control Framework for Soft Real-Time Applications on Multicore PlatformsIEEE Transactions on Computers10.1109/TC.2016.264096166:7(1247-1252)Online publication date: 1-Jul-2017
https://doi.org/10.1109/TC.2016.2640961
Blin ACourtaud CSopena JLawall JMuller G(2016)Maximizing Parallelism without Exploding Deadlines in a Mixed Criticality Embedded System2016 28th Euromicro Conference on Real-Time Systems (ECRTS)10.1109/ECRTS.2016.18(109-119)Online publication date: Jul-2016
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