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Architectural implications of hardware-accelerated bucket rendering on the PC

Published: 03 August 1997 Publication History
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References

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K. Akeley, "RealityEngineGraphies," Computer Graphics (Proe. Siggraph), Vol. 17, No. 3, August 1993, pp. 109- 116,
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M, Cox, Algorithms for Parallel Rendering, Ph.D. thesis, Princeton University, May 1995.
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D, Ellsworth, Polygon Rendering for Interactive Visualizations on Multicomputers, Ph.D. thesis, University of North Carolina at Chapel Hill, December 1996.
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J. Foley, A. van Dam, S. Feiner, J. Hughes, Computer Graphics: Principles and Practice, 2nd ed., Addison- Wesley, Reading MA, 1990.
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H. Fuchs, J. Poulton, J. Eyles, T. Greer, J. Goldfeather, D. Ellsworth, S. Molnar, G. Turk, B. Teggs, L. Israel, "Pixel- Planes 5: A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memories," Computer Graphics &roe. Siggraph), Vol. 23, No. 3, July 1989, pp. 79-88.
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Intel Corporation, Accelerated Graphics Port Interface Specification, revision 1.0, Intel Corporation, July 31, 1996.
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S. Molnar, J. Eyles, and J. Poulton, "PixelFlow: High- Speed Rendering Using Image Composition," Computer Graphics (Proe. Siggraph), Vol. 26, No. 2, July 1992, pp. 231-240.
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M. Kelley, S. Winner, K. Gould, "A Scaleable Hardware Render Accelerator using a Modified Scanline Algorithm," Computer Graphics (Proe. Siggraph), Vol. 26, No. 2, July 1992, pp. 241-248.
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  • (2011)Power gating strategies on GPUsACM Transactions on Architecture and Code Optimization10.1145/2019608.20196128:3(1-25)Online publication date: 18-Oct-2011
  • (2010)Exploration of tile/triangle-based rendering approaches for 3D graphics SoC2010 International Symposium on Next Generation Electronics10.1109/ISNE.2010.5669157(227-230)Online publication date: Nov-2010
  • (2010)Full system simulation with QEMU: An approach to multi-view 3D GPU designProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537690(3877-3880)Online publication date: May-2010
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cover image ACM Conferences
HWWS '97: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
August 1997
160 pages
ISBN:0897919610
DOI:10.1145/258694
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 03 August 1997

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Author Tags

  1. bucket rendering
  2. chunk rendering
  3. overlap
  4. tile rendering

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ESWGH97
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ESWGH97: The 1997 Eurographics/Siggraph Workshop on Graphics Hardware
August 3 - 4, 1997
California, Los Angeles, USA

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Overall Acceptance Rate 37 of 94 submissions, 39%

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Cited By

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  • (2011)Power gating strategies on GPUsACM Transactions on Architecture and Code Optimization10.1145/2019608.20196128:3(1-25)Online publication date: 18-Oct-2011
  • (2010)Exploration of tile/triangle-based rendering approaches for 3D graphics SoC2010 International Symposium on Next Generation Electronics10.1109/ISNE.2010.5669157(227-230)Online publication date: Nov-2010
  • (2010)Full system simulation with QEMU: An approach to multi-view 3D GPU designProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537690(3877-3880)Online publication date: May-2010
  • (2009)Parallel and Distributed Visualization AdvancesEncyclopedia of Information Science and Technology, Second Edition10.4018/978-1-60566-026-4.ch482(3018-3025)Online publication date: 2009
  • (2009)Methods for Precise False-Overlap Detection in Tile-Based RenderingProceedings of the 2009 International Conference on Computational Science and Engineering - Volume 0210.1109/CSE.2009.466(414-419)Online publication date: 29-Aug-2009
  • (2008)GRAALIEEE Computer Graphics and Applications10.1109/MCG.2008.7228:4(63-73)Online publication date: 1-Jul-2008
  • (2004)A load-balancing strategy for sort-first distributed renderingProceedings. 17th Brazilian Symposium on Computer Graphics and Image Processing10.1109/SIBGRA.2004.1352973(292-299)Online publication date: 2004
  • (2004)Efficient tile-aware bounding-box overlap test for tile-based rendering2004 International Symposium on System-on-Chip, 2004. Proceedings.10.1109/ISSOC.2004.1411177(165-172)Online publication date: 2004
  • (2004)Scene management models and overlap tests for tile-based renderingEuromicro Symposium on Digital System Design, 2004. DSD 2004.10.1109/DSD.2004.1333306(424-431)Online publication date: 2004
  • (2004)Memory Bandwidth Requirements of Tile-Based RenderingComputer Systems: Architectures, Modeling, and Simulation10.1007/978-3-540-27776-7_34(323-332)Online publication date: 2004
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