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A Brief Comment on “A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs” [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106]

Published: 21 January 2015 Publication History

Abstract

In the Ghiribaldi et al. [2013] paper, a complete self-testing and self configuring NoC infrastructure for cost-effective MPSoCs was presented in order to make NoC architecture tolerant to faults. To overcome the complexity involved during the complete reconfiguration of routing instances in the face of most of the usual failure patterns, Ghiribaldi et al. [2013] proposed a fast self-reconfiguration algorithm. The algorithm is based on segment-based routing implemented using Logic-Based Distributed Routing (LBDR) and claimed to have handled the most common NoC faults.
The purpose of this comment is to demonstrate the inconsistency of the fast self-configuration method presented in Ghiribaldi et al. [2013]. To handle inconsistency, we present the correct set of LBDR bits and also argue that complete reconfiguration of the routing instance is mandatory to handle some fault combinations. New coverage results of the fast self-reconfiguration algorithm of Ghiribaldi et al. [2013] are also presented.

References

[1]
A. Ghiribaldi, D. Ludovici, F. Triviño, A. Strano, J. Flich, J. L. Sánchez, F. Alfaro, M. Favalli, and D. Bertozzi. 2013. A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. ACM Trans. Embed. Comput. Syst. 12, 4 (July 2013), 106:1--106:29.
[2]
A. Mejia. 2008. Design and Implementation of Efficient Topology Agnostic Routing Algorithms for Interconnection Networks. Ph.D. Dissertation. University of Valencia.
[3]
A. Mejia, J. Flich, and J. Duato. 2008. On the potentials of segment-based routing for NoCs. In Proceedings of the 37th International Conference on Parallel Processing (ICPP’08). IEEE, 594--603.
[4]
S. Rodrigo, S. Medardoni, J. Flich, D. Bertozzi, and J. Duato. 2009. Efficient implementation of distributed routing algorithms for NoCs. IET Comput. Digital Techn. 3, 5 (2009), 460--475.
[5]
A. Strano, D. Bertozzi, F. Trivino, J. L. Sanchez, F. J. Alfaro, and J. Flich. 2012. OSR-Lite: Fast and deadlock-free NoC reconfiguration framework. In Proceedings of the International Conference on Embedded Computer Systems (SAMOS’12). 86--95.

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  • (2015)d2-LBDRProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755935(800-805)Online publication date: 9-Mar-2015

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  1. A Brief Comment on “A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs” [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106]

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    cover image ACM Transactions on Embedded Computing Systems
    ACM Transactions on Embedded Computing Systems  Volume 14, Issue 1
    January 2015
    443 pages
    ISSN:1539-9087
    EISSN:1558-3465
    DOI:10.1145/2724585
    Issue’s Table of Contents
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    Publication History

    Published: 21 January 2015
    Accepted: 01 September 2014
    Received: 01 August 2014
    Published in TECS Volume 14, Issue 1

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    Author Tags

    1. Network-on-Chip
    2. fault tolerance

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    • Spanish Ministerio de Economa y Competitividad (MINECO)
    • Indo-Spain DST project

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    • (2015)d2-LBDRProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755935(800-805)Online publication date: 9-Mar-2015

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