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WCET-Aware Dynamic D-cache Locking for A Single Task

Published: 04 June 2015 Publication History

Abstract

Caches have been extensively used to bridge the increasing speed gap between processors and off-chip memory. However, caches make it much harder to compute the WCET (Worst-Case Execution Time) of a program. Cache locking is an effective technique for overcoming the unpredictability problem of caches. We investigate the WCET aware D-cache locking problem for a single task, and propose two dynamic cache locking approaches. The first approach formulates the problem as a global ILP (Integer Linear Programming) problem that simultaneously selects a near-optimal set of variables as the locked cache contents and allocates them to the D-cache. The second one iteratively constructs a subgraph of the CFG of the task where the lengths of all the paths are close to the longest path length, and uses an ILP formulation to select a near-optimal set of variables in the subgraph as the locked cache contents and allocate them to the D-cache. For both approaches, we propose a novel, efficient D-cache allocation algorithm. We have implemented both approaches and compared them with the longest path-based, dynamic cache locking approach proposed in [22] and the static WCET analysis approach without cache locking proposed in [14] by using a set of benchmarks from the Mälardalen WCET benchmark suite, SNU real-time benchmarks and the benchmarks used in [27]. Compared to the static WCET analysis approach, the average WCET improvements of the first approach range between 11.3% and 31.6%, and the average WCET improvements of the second approach range between 12.3% and 32.9%. Compared to the longest path-based, dynamic cache locking approach, the average WCET improvements of the first approach range between 4.7% and 14.3%, and the average WCET improvements of the second approach range between 5.3% and 15.0%.

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Cited By

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  • (2024)Duration-based Instruction Cache Locking2024 IEEE 30th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA62462.2024.00021(85-90)Online publication date: 21-Aug-2024
  • (2023)Pin or Fuse? Exploiting Scratchpad Memory to Reduce Off-Chip Data Transfer in DNN AcceleratorsProceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization10.1145/3579990.3580017(224-235)Online publication date: 17-Feb-2023
  • (2020)Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data CachesIEEE Access10.1109/ACCESS.2020.30321458(192379-192392)Online publication date: 2020
  • Show More Cited By

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cover image ACM Conferences
LCTES'15: Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM
June 2015
149 pages
ISBN:9781450332576
DOI:10.1145/2670529
  • cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 50, Issue 5
    LCTES '15
    May 2015
    141 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/2808704
    • Editor:
    • Andy Gill
    Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 04 June 2015

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Author Tags

  1. Worst-case execution time
  2. dynamic data cache locking
  3. false dependency
  4. graph orientation
  5. integer linear programming
  6. interference graph

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Cited By

View all
  • (2024)Duration-based Instruction Cache Locking2024 IEEE 30th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA62462.2024.00021(85-90)Online publication date: 21-Aug-2024
  • (2023)Pin or Fuse? Exploiting Scratchpad Memory to Reduce Off-Chip Data Transfer in DNN AcceleratorsProceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization10.1145/3579990.3580017(224-235)Online publication date: 17-Feb-2023
  • (2020)Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data CachesIEEE Access10.1109/ACCESS.2020.30321458(192379-192392)Online publication date: 2020
  • (2017)Integrating task scheduling and cache locking for multicore real-time embedded systemsACM SIGPLAN Notices10.1145/3140582.308103352:5(71-80)Online publication date: 21-Jun-2017
  • (2017)Integrating task scheduling and cache locking for multicore real-time embedded systemsProceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3078633.3081033(71-80)Online publication date: 21-Jun-2017
  • (2017)WCET-Aware Dynamic I-Cache Locking for a Single TaskACM Transactions on Architecture and Code Optimization10.1145/304668314:1(1-26)Online publication date: 13-Mar-2017
  • (2017)Dynamic Data-Cache Locking for Minimizing the WCET of a Single TaskACM Transactions on Embedded Computing Systems10.1145/299460216:2(1-29)Online publication date: 2-Jan-2017
  • (2016)A Survey of Techniques for Cache LockingACM Transactions on Design Automation of Electronic Systems10.1145/285879221:3(1-24)Online publication date: 16-May-2016

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