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Dynamic Data-Cache Locking for Minimizing the WCET of a Single Task

Published: 02 January 2017 Publication History

Abstract

Caches have been widely used in modern embedded processors to bridge the increasing speed gap between processors and off-chip memory. In real-time embedded systems, computing the Worst-Case Execution Time (WCET) of a task is essential for the task scheduler to construct a valid schedule for a task set. Unfortunately, caches make it much harder to compute the WCET of a task. Cache locking has been proposed to alleviate the timing unpredictability problem caused by caches. In this article, we investigate the following WCET-aware data-cache locking problem for a single task. Given a task, select a set of variables as locked cache contents such that the WCET of the task is minimized. We propose two dynamic full cache-locking approaches. The first formulates the problem as a global Integer Linear Programming (ILP) problem that simultaneously selects a minimum set of memory blocks of variables as locked cache contents and allocates them to the data cache. The second iteratively constructs a subgraph of the Control Flow Graph (CFG) of the task in which the lengths of all the paths are close to the longest path length, uses an ILP formulation to select a minimum set of memory blocks of variables in the subgraph as locked cache contents, and allocates the selected memory blocks to the data cache. We also propose two novel, efficient data-cache allocation algorithms for the global ILP approach and the iterative ILP approach, respectively. We have implemented both approaches and compared them with two state-of-the-art approaches, the longest path-based dynamic cache-locking approach and the static WCET analysis approach without cache locking by using a set of benchmarks from the Mälardalen WCET benchmark suite, SNU real-time benchmarks, and Powerstone benchmarks. Compared to the static WCET analysis approach, the average WCET improvements of the first approach range between 11.4% and 26.4%. Compared to the longest path--based, dynamic cache-locking approach, the average WCET improvements of the first approach range between 5.0% and 15.4%. The second approach performs slightly better than the first approach.

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        cover image ACM Transactions on Embedded Computing Systems
        ACM Transactions on Embedded Computing Systems  Volume 16, Issue 2
        Special Issue on LCETES 2015, Special Issue on ACSD 2015 and Special Issue on Embedded Devise Forensics and Security
        May 2017
        705 pages
        ISSN:1539-9087
        EISSN:1558-3465
        DOI:10.1145/3025020
        Issue’s Table of Contents
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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        Publication History

        Published: 02 January 2017
        Accepted: 01 September 2016
        Revised: 01 September 2016
        Received: 01 May 2016
        Published in TECS Volume 16, Issue 2

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        Author Tags

        1. Worst-case execution time
        2. dynamic data-cache locking
        3. false dependency
        4. graph orientation
        5. integer linear programming
        6. interference graph

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        • (2023)Efficient Token-Guided Image-Text Retrieval With Consistent Multimodal Contrastive TrainingIEEE Transactions on Image Processing10.1109/TIP.2023.328671032(3622-3633)Online publication date: 1-Jan-2023
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        • (2020)A Dynamic Instruction Cache Locking Approach for Minimizing Worst Case Execution Time of a Single TaskIEEE Access10.1109/ACCESS.2020.30381708(208003-208015)Online publication date: 2020
        • (2019)WCET-aware hyper-block construction for clustered VLIW processorsProceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3316482.3326349(110-122)Online publication date: 23-Jun-2019
        • (2017)An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW ProcessorsACM Transactions on Embedded Computing Systems10.1145/312652416:5s(1-21)Online publication date: 27-Sep-2017
        • (2017)WCET-Aware Dynamic I-Cache Locking for a Single TaskACM Transactions on Architecture and Code Optimization10.1145/304668314:1(1-26)Online publication date: 13-Mar-2017

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