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VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping

Published: 19 June 2016 Publication History

Abstract

Simulation is the most common approach to evaluate Network on Chip (NoC) designs and many simulators at different abstraction levels have been developed so far. However, researchers have to spend a considerable amount of time and effort to debug, analyze, and extract meaningful information from the simulator reports. In this work, we propose a full-system visualization framework, called VisualNoC, that support both network simulation and task mapping. VisualNoC operates in a cycle-accurate mode and is based on an event-based trace model which can record the behaviors of routers, processing elements and packets. The visualization interface can provide efficient debugging and analysis platform by representing the simulation process and results in a variety of ways. One of the main features of VisualNoC is providing an intuitive way of analyzing the efficiency of different mapping algorithms that helps in finding bottlenecks and optimizing the design.

References

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Cited By

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  • (2023)Visual Exploratory Analysis for Designing Large-Scale Network-on-Chip Architectures: A Domain Expert-Led Design StudyIEEE Transactions on Visualization and Computer Graphics10.1109/TVCG.2023.333717330:4(1970-1983)Online publication date: 28-Nov-2023
  • (2021)A Lego-Based Neural Network Design Methodology With Flexible NoCIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2021.312539911:4(711-724)Online publication date: Dec-2021
  • (2020)ECDR2: Error Corrector and Detector Relocation Router for Network-on-ChipIEEE Transactions on Computers10.1109/TC.2020.2991749(1-1)Online publication date: 2020
  • Show More Cited By

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cover image ACM Other conferences
MES '16: Proceedings of the Third ACM International Workshop on Many-core Embedded Systems
June 2016
35 pages
ISBN:9781450342629
DOI:10.1145/2934495
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • Univ. Turku: University of Turku

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 June 2016

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Author Tags

  1. Debug
  2. Many-Core System
  3. Mapping Algorithm
  4. Network-on-Chip
  5. Statistics
  6. Visualization Simulator

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  • Refereed limited

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MES '16

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Overall Acceptance Rate 5 of 21 submissions, 24%

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Cited By

View all
  • (2023)Visual Exploratory Analysis for Designing Large-Scale Network-on-Chip Architectures: A Domain Expert-Led Design StudyIEEE Transactions on Visualization and Computer Graphics10.1109/TVCG.2023.333717330:4(1970-1983)Online publication date: 28-Nov-2023
  • (2021)A Lego-Based Neural Network Design Methodology With Flexible NoCIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2021.312539911:4(711-724)Online publication date: Dec-2021
  • (2020)ECDR2: Error Corrector and Detector Relocation Router for Network-on-ChipIEEE Transactions on Computers10.1109/TC.2020.2991749(1-1)Online publication date: 2020
  • (2020)A NoC-based simulator for design and evaluation of deep neural networksMicroprocessors & Microsystems10.1016/j.micpro.2020.10314577:COnline publication date: 1-Sep-2020
  • (2019)Efficient Design-for-Test Approach for Networks-on-ChipIEEE Transactions on Computers10.1109/TC.2018.286594868:2(198-213)Online publication date: 17-Jul-2019
  • (2018)Optimizing dynamic mapping techniques for on-line NoC testProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201655(227-232)Online publication date: 22-Jan-2018
  • (2018)A lifetime-aware mapping algorithm to extend MTTF of networks-on-chipProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201638(147-152)Online publication date: 22-Jan-2018
  • (2018)Optimizing dynamic mapping techniques for on-line NoC test2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297310(227-232)Online publication date: Jan-2018
  • (2018)A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297297(147-152)Online publication date: Jan-2018
  • (2017)Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGAACM Transactions on Reconfigurable Technology and Systems10.1145/315175810:4(1-27)Online publication date: 13-Dec-2017

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