research-article

Public Access

RAPID Programming of Pattern-Recognition Processors

Authors:

Kevin Angstadt,

Westley Weimer,

Kevin SkadronAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 44, Issue 2

Pages 593 - 605

https://doi.org/10.1145/2980024.2872393

Published: 25 March 2016 Publication History

Abstract

We present RAPID, a high-level programming language and combined imperative and declarative model for programming pattern-recognition processors, such as Micron's Automata Processor (AP). The AP is a novel, non-Von Neumann architecture for direct execution of non-deterministic finite automata (NFAs), and has been demonstrated to provide substantial speedup for a variety of data-processing applications. RAPID is clear, maintainable, concise, and efficient both at compile and run time. Language features, such as code abstraction and parallel control structures, map well to pattern-matching problems, providing clarity and maintainability. For generation of efficient runtime code, we present algorithms to convert RAPID programs into finite automata. Further, we introduce a tessellation technique for configuring the AP, which significantly reduces compile time, increases programmer productivity, and improves maintainability. We evaluate five RAPID programs against custom, baseline implementations previously demonstrated to be significantly accelerated by the AP. We find that RAPID programs are much shorter in length, are expressible at a higher level of abstraction than their handcrafted counterparts, and yield generated code that is often more compact. In addition, our tessellation technique for configuring the AP has comparable device utilization to, and results in compilation that is up to four orders of magnitude faster than, current solutions.

References

[1]

R. Alur, P. Cerný, P. Madhusudan, and W. Nam. Synthesis of interface specifications for Java classes. In Proceedings of the 32nd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, pages 98--109, 2005.

Digital Library

[2]

G. Ammons, D. Mandelin, R. Bodık, and J. R. Larus. Debugging temporal specifications with concept analysis. In Proceedings of the 2003 ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 182--195, 2003.

Digital Library

[3]

K. R. Apt, J. Brunekreef, V. Partington, and A. Schaerf. Alma-0: An imperative language that supports declarative programming. Technical report, 1997.

[4]

C. Bo, K. Wang, Y. Qi, and K. Skadron. String kernel testing acceleration using the Micron Automata Processor. In Workshop on Computer Architecture for Machine Learning, 2015.

[5]

Capgemini. Big & fast data : The rise of insight-driven business. http://www.capgemini.com/resource-file-access/resource/pdf/big_fast_data_the_rise_of_insight-driven_business-report.pdf, 2015.

[6]

P. Caron and D. Ziadi. Characterization of Glushkov automata. Theoretical Computer Science, 233(1):75--90, 2000.

Digital Library

[7]

H. D. Cheng and K. S. Fu. VLSI architectures for string matching and pattern matching. Pattern Recognition, 20(1):125--144, 1987.

Digital Library

[8]

Computer Sciences Corporation. Big data universe beginning to explode. http://www.csc.com/insights/flxwd/78931-big_data_universe_beginning_to_explode, 2012.

[9]

E. W. Dijkstra. Guarded commands, nondeterminacy and formal derivation of programs. Communications of the ACM, 18(8):453--457, 1975.

Digital Library

[10]

P. Dlugosch, D. Brown, P. Glendenning, M. Leventhal, and H. Noyes. An efficient and scalable semiconductor architecture for parallel automata processing. IEEE Transactions on Parallel and Distributed Systems, 25(12):3088--3098, 2014.

[11]

A. Halaas. A systolic VLSI matrix for a family of fundamental searching problems. Integration VLSI Journal, 1(4):269--282, 1983.

Digital Library

[12]

A. Halaas, B. Svingen, M. Nedland, P. Sætrom, O. Snøve, Jr., and O. R. Birkeland. A recursive MISD architecture for pattern matching. IEEE Transactions on Very Large Scale Integrated Systems, 12(7):727--734, 2004.

Digital Library

[13]

A. Krishna, T. Heil, N. Lindberg, F. Toussi, and S. VanderWiel. Hardware acceleration in the IBM PowerEN processor: Architecture and performance. In Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques, pages 389--400, 2012.

Digital Library

[14]

M. E. Lesk and E. Schmidt. Lex: A lexical analyzer generator. Technical Report 39, AT&T Bell Laboratories Computing Science, 1975.

[15]

H. Lu, K. Zheng, B. Liu, X. Zhang, and Y. Liu. A memory-efficient parallel string matching architecture for high-speed intrusion detection. IEEE Journal on Selected Areas in Communications, 24(10):1793--1804, 2006.

Digital Library

[16]

S. McCanne and V. Jacobson. The BSD packet filter: A new architecture for user-level packet capture. In Proceedings of the 1993 USENIX Winter Conference, USENIX'93, pages 295--270, 1993.

[17]

Micron Technoloy. Calculating Hamming distance. http://www.micronautomata.com/documentation/cookbook/c_hamming_distance.html.

[18]

I. Roy and S. Aluru. Finding motifs in biological sequences using the Micron Automata Processor. In Proceedings of the 28th IEEE International Parallel and Distributed Processing Symposium, pages 415--424, 2014.

Digital Library

[19]

W. Thies, M. Karczmarek, and S. P. Amarasinghe. StreamIt: A language for streaming applications. In Proceedings of the 11th International Conference on Compiler Construction, pages 179--196. Springer-Verlag, 2002.

Digital Library

[20]

Titan IC Systems. RXP regular eXpression processor soft IP. http://titanicsystems.com/Products/Regular-eXpression-Processor-(RXP).

[21]

K. Wang, M. Stan, and K. Skadron. Association rule mining with the Micron Automata Processor. In Proceedings of the 29th IEEE International Parallel & Distributed Processing Symposium, 2015.

Digital Library

[22]

H. Yamada, M. Hirata, H. Nagai, and K. Takahashi. A high-speed string-search engine. IEEE Journal of Solid-State Circuits, 22(5):829--834, 1987.

[23]

K. Zhou, J. J. Fox, K. Wang, D. E. Brown, and K. Skadron. Brill tagging on the Micron Automata Processor. In Proceedings of the 9th IEEE International Conference on Semantic Computing, pages 236--239, 2015.

Cited By

Monteiro ERighi RKunst Rda Costa CSingh D(2020)Combining Natural Language Processing and Blockchain for Smart Contract Generation in the Accounting and Legal FieldIntelligent Human Computer Interaction10.1007/978-3-030-68449-5_31(307-321)Online publication date: 24-Nov-2020
https://dl.acm.org/doi/10.1007/978-3-030-68449-5_31
Nguyen TBecchi M(2024)A Transducers-based Programming Framework for Efficient Data TransformationProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676891(66-77)Online publication date: 14-Oct-2024
https://dl.acm.org/doi/10.1145/3656019.3676891
Ge TZhang TLiu HTsafrir DMUSUVATHI MGupta RAbu-Ghazaleh N(2024)ngAP: Non-blocking Large-scale Automata Processing on GPUsProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 110.1145/3617232.3624848(268-285)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3617232.3624848
Show More Cited By

Index Terms

RAPID Programming of Pattern-Recognition Processors

Recommendations

RAPID Programming of Pattern-Recognition Processors
ASPLOS '16

We present RAPID, a high-level programming language and combined imperative and declarative model for programming pattern-recognition processors, such as Micron's Automata Processor (AP). The AP is a novel, non-Von Neumann architecture for direct ...
RAPID Programming of Pattern-Recognition Processors
ASPLOS '16: Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems

We present RAPID, a high-level programming language and combined imperative and declarative model for programming pattern-recognition processors, such as Micron's Automata Processor (AP). The AP is a novel, non-Von Neumann architecture for direct ...
Realizing parallelism in quantum MISD architecture
CF '19: Proceedings of the 16th ACM International Conference on Computing Frontiers

We propose an idea to speed up instruction execution through a probabilistic approach, using the parallelism offered by quantum computers. For this, we divide the instruction set of an arbitrary quantum instruction set architecture (QISA) into separate ...

Comments

Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 44, Issue 2

ASPLOS'16

May 2016

774 pages

ISSN:0163-5964

DOI:10.1145/2980024

Editor:
Doug DeGroot
acm dot org

Issue’s Table of Contents

ASPLOS '16: Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems
March 2016
824 pages
ISBN:9781450340915
DOI:10.1145/2872362
General Chair:
Tom Conte
Georgia Tech, USA
,
Program Chair:
Yuanyuan Zhou
University of California, San Diego, USA

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 March 2016

Published in SIGARCH Volume 44, Issue 2

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

24
Total Citations
View Citations
950
Total Downloads

Downloads (Last 12 months)104
Downloads (Last 6 weeks)24

Reflects downloads up to 15 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Monteiro ERighi RKunst Rda Costa CSingh D(2020)Combining Natural Language Processing and Blockchain for Smart Contract Generation in the Accounting and Legal FieldIntelligent Human Computer Interaction10.1007/978-3-030-68449-5_31(307-321)Online publication date: 24-Nov-2020
https://dl.acm.org/doi/10.1007/978-3-030-68449-5_31
Nguyen TBecchi M(2024)A Transducers-based Programming Framework for Efficient Data TransformationProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676891(66-77)Online publication date: 14-Oct-2024
https://dl.acm.org/doi/10.1145/3656019.3676891
Ge TZhang TLiu HTsafrir DMUSUVATHI MGupta RAbu-Ghazaleh N(2024)ngAP: Non-blocking Large-scale Automata Processing on GPUsProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 110.1145/3617232.3624848(268-285)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3617232.3624848
Yu JLebdeh MNguyen HTaouil MHamdioui S(2022)APmap: An Open-Source Compiler for Automata ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.306232841:1(196-200)Online publication date: Jan-2022
https://doi.org/10.1109/TCAD.2021.3062328
Clark JDemirag DMoosavi S(2020)Demystifying StablecoinsQueue10.1145/3387945.338878118:1(39-60)Online publication date: 16-Mar-2020
https://dl.acm.org/doi/10.1145/3387945.3388781
Hawkins S(2020)Algorithm 1009ACM Transactions on Mathematical Software10.1145/338153746:2(1-28)Online publication date: 19-May-2020
https://dl.acm.org/doi/10.1145/3381537
Brisebarre NJoldeş MMuller JNaneş APicot J(2020)Error Analysis of Some Operations Involved in the Cooley-Tukey Fast Fourier TransformACM Transactions on Mathematical Software10.1145/336861946:2(1-27)Online publication date: 19-May-2020
https://dl.acm.org/doi/10.1145/3368619
Dinh VNguyen XLee H(2019)A Novel FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation and CompensationACM Transactions on Reconfigurable Technology and Systems10.1145/332248212:2(1-21)Online publication date: 30-May-2019
https://dl.acm.org/doi/10.1145/3322482
Oppermann JReuter-Oppermann MSommer LKoch ASinnen O(2019)Exact and Practical Modulo Scheduling for High-Level SynthesisACM Transactions on Reconfigurable Technology and Systems10.1145/331767012:2(1-26)Online publication date: 6-May-2019
https://dl.acm.org/doi/10.1145/3317670
Bo CDang VXie TWadden JStan MSkadron K(2019)Automata Processing in Reconfigurable ArchitecturesACM Transactions on Reconfigurable Technology and Systems10.1145/331457612:2(1-25)Online publication date: 17-May-2019
https://dl.acm.org/doi/10.1145/3314576
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents