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Exploiting Data Longevity for Enhancing the Lifetime of Flash-based Storage Class Memory

Published: 13 June 2017 Publication History

Abstract

Storage-class memory (SCM) combines the benefits of a solid-state memory, such as high-performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Among candidate solid-state nonvolatile memory technologies that could potentially be used to construct SCM, flash memory is a well-established technology and have been widely used in commercially available SCM incarnations. Flash-based SCM enables much better tradeoffs between performance, space and power than disk-based systems. However, write endurance is a significant challenge for a flash-based SCM (each act of writing a bit may slightly damage a cell, so one flash cell can be written 10^4-10^5 times, depending on the flash technology, before it becomes unusable). This is a well-documented problem and has received a lot of attention by manufactures that are using some combination of write reduction and wear-leveling techniques for achieving longer lifetime. In an effort to improve flash lifetime, first, by quantifying data longevity in an SCM, we show that a majority of the data stored in a solid-state SCM do not require long retention times provided by flash memory (i.e., up to 10 years in modern devices); second, by exploiting retention time relaxation, we propose a novel mechanism, called Dense-SLC (D-SLC), which enables us perform multiple writes into a cell during each erase cycle for lifetime extension; and finally, we discuss the required changes in the flash management software (FTL) in order to use D-SLC mechanism for extending the lifetime of the solid-state part of an SCM. Using an extensive simulation-based analysis of an SLC flash-based SCM, we demonstrate that D-SLC is able to significantly improve device lifetime (between 5.1X and 8.6X) with no performance overhead and also very small changes at the FTL software.

References

[1]
Nitin Agrawal, Vijayan Prabhakaran, Ted Wobber, John D. Davis, Mark Manasse, and Rina Panigrahy. 2008. Design Tradeoffs for SSD Performance. In USENIX ATC. http://www.microsoft.com/en-us/download/details.aspx?id=52332.
[2]
Frank Berry. 2015. 2015 Enterprise Flash Storage. In Flash Memory Summit
[3]
John S. Bucy, Jiri Schindler, Steven W. Schlosser, and Gregory R. Ganger. 2008. The DiskSim Simulation Environment Version 4.0 Reference Manual. In Carnegie Mellon University-PDL-08--101. http://www.pdl.cmu.edu/DiskSim/.
[4]
G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy. 2008. Overview of Candidate Device Technologies for Storage-Class Memory. In IBM Journal of Research and Development, Vol. 52, Issue. 4.5.
[5]
Werner Bux and Ilias Iliadis. 2010. Performance of Greedy Garbage Collection in Flash-based Solid-State Drives. In Journal of Performance Evaluation, VOL. 67, Issue. 11.
[6]
Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch, Ken Mai, and Onur Mutlu. 2015. Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery. In DSN.
[7]
Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, and Onur Mutlu. 2015. Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery. In HPCA.
[8]
Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Osman Unsal, Adrian Cristal, and Ken Mai. 2014. Neighbor-Cell Assisted Error Correction for MLC NAND Flash Memories. In SIGMETRICS.
[9]
Feng Chen, David A. Koufaty, and Xiaodong Zhang. 2009. Understanding Intrinsic Characteristics and System Implications of Flash Memory Based Solid State Drives. In SIGMETRICS.
[10]
R. F. Freitas and W. W. Wilcke. 2008. Storage-Class Memory: The Next Storage System Technology. In IBM Journal of Research and Development, Vol. 52, Issue. 4.5.
[11]
Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, and Jack K. Wolf. 2009. Characterizing Flash Memory: Anomalies, Observations, and Applications. In MICRO.
[12]
Jim Handy. 2016. Flash Technology: Annual Update. In Flash Memory Summit.
[13]
Benny Van Houdt. 2013. A Mean Field Model for a Class of Garbage Collection Algorithms in Flash based Solid State Drives. In SIGMETRICS.
[14]
Benny Van Houdt. 2013. Performance of Garbage Collection Algorithms for Flash-based Solid State Drives with Hot/Cold Data. In Journal of Performance Evaluation, VOL. 70, Issue 10.
[15]
Jaeyong Jeong, Sangwook Hahn, Sungjin Lee, and Jihong Kim. 2014. Lifetime Improvement of NAND Flash-based Storage Systems Using Dynamic Program and Erase Scaling. In USENIX FAST.
[16]
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, N. Vijaykrishnan, Ravishankar Iyer, and Chita R. Das. 2012. Cache Revive: Architecting Volatile STT-RAM Caches for Enhanced Performance in CMPs . In DAC.
[17]
Myoungsoo Jung and Mahmut Kandemir. 2012. An Evaluation of Different Page Allocation Strategies on High-Speed SSDs. In USENIX HotStorage.
[18]
Myoungsoo Jung and Mahmut Kandemir. 2013. Revisiting Widely Held SSD Expectations and Rethinking System-Level Implications. In SIGMETRICS.
[19]
Jae-Duk Lee, Jeong-Hyuk Choi, Donggun Park, and Kinam Kim. 2003. Degradation of Tunnel Oxide by FN Current Stress and Its Effects on Data Retention Characteristics of 90-nm NAND Flash Memory. In IRPS.
[20]
Yongkun Li, Patrick P. C. Lee, and John C. S. Lui. 2013. Stochastic Modeling of Large-Scale Solid-State Storage Systems: Analysis, Design Tradeoffs and Optimization. In SIGMETRICS.
[21]
Ren-Shuo Liu, Chia-Lin Yang, and Wei Wu. 2012. Optimizing NAND Flash-Based SSDs via Retention Relaxation. In USENIX FAST.
[22]
Yixin Luo, Yu Cai, Saugata Ghose, Jongmoo Choi, and Onur Mutlu. 2015. WARM: Improving NAND Flash Memory Lifetime with Write-hotness Aware Retention Management. In MSST.
[23]
Fabio Margaglia, Gala Yadgar, Eitan Yaakobi, Yue Li, Assaf Schuster, and Andre Brinkmann. 2016. The Devil Is in the Details: Implementing Flash Page Reuse with WOM Codes. In USENIX FAST.
[24]
Justin Meza, Qiang Wu, Sanjeev Kumar, and Onur Mutlu. 2015. A Large-Scale Study of Flash Memory Failures in the Field. In SIGMETRICS.
[25]
Micron. 2014. NAND Flash Memory MT29F32G08ABAAA, MT29F64G08AFAAA, MT29F128G08A{J/K/M}AAA, MT29F256G08AUAAA, MT29F32G08ABCAB, MT29F64G08AECAB, MT29F128G08A{K/M}CAB, MT29F256G08AUCAB.
[26]
Neal Mielke, Hanmant Belgal, Ivan Kalastirsky, Pranav Kalavade, Andrew Kurtz, Qingru Meng, Nick Righos, and Jie Wu. 2004. Flash EEPROM Threshold Instabilities due to Charge Trapping During Program/Erase Cycling. In IEEE Transactions on Device and Materials Reliability, Vol. 4, No. 3.
[27]
Dushyanth Narayanan, Austin Donnelly, and Antory Rowstron. 2008. Write Off-Loading: Practical Power Management for Enterprise Storage. In USENIX FAST. http://iotta.snia.org/traces/388.
[28]
Yangyang Pan, Guiqiang Dong, Qi Wu, and Tong Zhang. 2012. Quasi-Nonvolatile SSD: Trading Flash Memory Nonvolatility to Improve Storage System Performance for Enterprise Applications. In HPCA.
[29]
Thomas Parnell. 2016. NAND Flash Basics and Error Characteristics. In Flash Memory Summit.
[30]
Moinuddin K. Qureshi, Sudhanva Gurumurthi, and Bipin Rajendran. 2011. Phase Change Memory: From Devices to Systems. Morgan & Claypool Publisher
[31]
Clinton Wills Smullen, Vidyabhushan Mohan, Anurag Nigam, Sudhanva Gurumurthi, and Mircea R. Stan. 2011. Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches. In HPCA.
[32]
KangDeug Suh, Byung-Hoon Suh, Young-Ho Lim, Jin-Ki Kim, Young-Joon Choi, Yong-Nam Koh, Sung Soo Lee, Suk-Chon Kwon, Byung-Soon Choi, Jin-Sun Yum, Jung-Hyuk Choi, Jang-Rae Kim, and Hyung-Kyu Lim. 1995. A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme. In ISSCC.
[33]
Yuan Xie. 2011. Modeling, Architecture, and Applications for Emerging Memory Technologies. In IEEE Design and Test Computers, Vol. 28, No. 1.
[34]
Jie Zhang, Gieseo Park, David Donofrio, Mustafa Shihab, John Shalf, and Myoungsoo Jung. 2015. OpenNVM: An Open-Sourced FPGA-based NVM Controller for Low Level Memory Characterization. In ICCD

Cited By

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  • (2024) Operation Scheme Optimizations to Achieve Ultrahigh Endurance (10 10 ) in Flash Memory IEEE Transactions on Electron Devices10.1109/TED.2024.340540071:11(7195-7198)Online publication date: Nov-2024
  • (2024)Midas Touch: Invalid-Data Assisted Reliability and Performance Boost for 3d High-Density Flash2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00057(657-670)Online publication date: 2-Mar-2024

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cover image Proceedings of the ACM on Measurement and Analysis of Computing Systems
Proceedings of the ACM on Measurement and Analysis of Computing Systems  Volume 1, Issue 1
June 2017
712 pages
EISSN:2476-1249
DOI:10.1145/3107080
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 13 June 2017
Published in POMACS Volume 1, Issue 1

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Author Tags

  1. lifetime
  2. retention time
  3. slc flash memory
  4. ssd

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View all
  • (2024) Operation Scheme Optimizations to Achieve Ultrahigh Endurance (10 10 ) in Flash Memory IEEE Transactions on Electron Devices10.1109/TED.2024.340540071:11(7195-7198)Online publication date: Nov-2024
  • (2024)Midas Touch: Invalid-Data Assisted Reliability and Performance Boost for 3d High-Density Flash2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00057(657-670)Online publication date: 2-Mar-2024

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