research-article

Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in freeRTOS applications

Authors:

Ádria Barros de Oliveira,

Gennaro Severino Rodrigues,

Fernanda Lima KastensmidtAuthors Info & Claims

SBCCI '17: Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands

Pages 84 - 89

https://doi.org/10.1145/3109984.3110008

Published: 28 August 2017 Publication History

Abstract

This paper evaluates the efficiency and performance impact of a dual-core lockstep as a method for fault-tolerance running on top of FreeRTOS applications. The method was implemented on a dual-core ARM Cortez-A9 processor embedded into the Zynq-7000 APSoC. Fault injection experiments show that the method can mitigate up to 63% on the FreeRTOS applications. This result is very near to the mitigation achievable on bare-metal. Results also show that the overhead caused by the method is higher on FreeRTOS application than it is on bare-metal.

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Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in freeRTOS applications
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cover image ACM Conferences

SBCCI '17: Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands

August 2017

238 pages

ISBN:9781450351065

DOI:10.1145/3109984

General Chair:
Jarbas A. N. Silveira
UFC - Brazil

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 28 August 2017

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SBCCI '17: 30th Symposium on Integrated Circuits and Systems Design

August 28 - September 1, 2017

Ceará, Fortaleza, Brazil

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https://doi.org/10.1109/TETC.2022.3205808
Gizopoulos DPapadimitriou GChatzopoulos O(2023)Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and Microarchitectures2023 IEEE International Test Conference (ITC)10.1109/ITC51656.2023.00056(377-382)Online publication date: 7-Oct-2023
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