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An architectural solution for the inductive noise problem due to clock-gating

Authors:

Mondira Deb Pant,

Pankaj Pant,

D. Scott Wills,

Vivek TiwariAuthors Info & Claims

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

Pages 255 - 257

https://doi.org/10.1145/313817.313938

Published: 17 August 1999 Publication History

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References

[1]

BAKOGLU, H. B. Circuits, lnterconnections and Packaging for VLSI. Addison-Wesley, 1990.

Google Scholar

[2]

BURGER, D., AND AUSTIN, T. M. The SimpleScalar tool set, version 2.0. Tech. Rep. 1342, Univ. of Wisconsin-Madison Computer Science Department, June 1997.

Google Scholar

[3]

CHANG, Y.-S., GUPTA, S. K., AND BREUER, M. A. Anaylsis of ground bounce in deep sub-micron circuits. In VLSI Test Symposium (1997), IEEE, IEEE Computer Society Press, pp. 110-116.

Digital Library

Google Scholar

[4]

OHNSON, H. W., AND GRAHAM, M. High speed Digital Design: A Handbook of Black Magic. Prentice Hall, January 1993.

Digital Library

Google Scholar

[5]

SENTHINATHAN, R., AND PRINCE, J.L. Simultaneous switching ground noise calculation for packaged CMOS devices. IEEE Journal of Solid-State Circuits 26, 11 (Nov 1991), 1724-1728.

Crossref

Google Scholar

[6]

TIWARI, V., SINGH, D., RAJAGOPAL, S., MEHTA, G., PA- TEL, R., AND BAEZ, F. Reduing power in high-performance microprocessors. In Design Automation Conference (June 1998), pp. 732-737.

Digital Library

Google Scholar

Cited By

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Bhattacharjee PTrivedi GMajumder A(2022)On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategiesInternational Journal of Electronics10.1080/00207217.2022.2158493111:1(184-203)Online publication date: 28-Dec-2022
https://doi.org/10.1080/00207217.2022.2158493
Gao YYang AJiang J(2021)A study and design of digital circuit2021 International Conference on Electronic Information Engineering and Computer Science (EIECS)10.1109/EIECS53707.2021.9588061(848-854)Online publication date: 23-Sep-2021
https://doi.org/10.1109/EIECS53707.2021.9588061
P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)Power Noise Reduction TechniquesOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_32(501-509)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_32
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Index Terms

An architectural solution for the inductive noise problem due to clock-gating
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Emerging technologies

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Published In

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

August 1999

295 pages

ISBN:158113133X

DOI:10.1145/313817

Chairmen:
Farid N. Najim
Univ. of Illinois at Urbana-Champaign
,
Jason Cong
UCLA
,
David Blaauw
Motorola

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 August 1999

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ISLPED99

Sponsor:

SIGDA
IEEE-CAS

ISLPED99: International Symposium on Low Power Electronics and Design

August 16 - 17, 1999

California, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Bhattacharjee PTrivedi GMajumder A(2022)On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategiesInternational Journal of Electronics10.1080/00207217.2022.2158493111:1(184-203)Online publication date: 28-Dec-2022
https://doi.org/10.1080/00207217.2022.2158493
Gao YYang AJiang J(2021)A study and design of digital circuit2021 International Conference on Electronic Information Engineering and Computer Science (EIECS)10.1109/EIECS53707.2021.9588061(848-854)Online publication date: 23-Sep-2021
https://doi.org/10.1109/EIECS53707.2021.9588061
P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)Power Noise Reduction TechniquesOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_32(501-509)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_32
Bertran RBuyuktosunoglu ABose PSlegel TSalem GCarey SRizzolo RStrach TFlautner KWenisch TOzer EFerdman M(2014)Voltage Noise in Multi-Core ProcessorsProceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2014.12(368-380)Online publication date: 13-Dec-2014
https://dl.acm.org/doi/10.1109/MICRO.2014.12
Kim YJohn LPaul IManne SSchulte MHenkel J(2013)Performance boosting under reliability and power constraintsProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561896(334-341)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561896
Reddi VGupta M(2013)Resilient Architecture Design for Voltage VariationSynthesis Lectures on Computer Architecture10.2200/S00486ED1V01Y201303CAC0228:2(1-138)Online publication date: 29-May-2013
https://doi.org/10.2200/S00486ED1V01Y201303CAC022
Kim YJohn LPant SManne SSchulte MBircher WGovindan M(2012)AUDITProceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2012.28(212-223)Online publication date: 1-Dec-2012
https://dl.acm.org/doi/10.1109/MICRO.2012.28
Yeh CChang KChen TYeh C(2011)Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategyACM Transactions on Architecture and Code Optimization10.1145/2019608.20196158:3(1-27)Online publication date: 18-Oct-2011
https://dl.acm.org/doi/10.1145/2019608.2019615
Fan XKrstic MWolf CGrass E(2011)GALS Design for On-chip Ground Bounce SuppressionProceedings of the 2011 17th IEEE International Symposium on Asynchronous Circuits and Systems10.1109/ASYNC.2011.11(43-52)Online publication date: 27-Apr-2011
https://dl.acm.org/doi/10.1109/ASYNC.2011.11
Chowdhury MKhaled PGjanci J(2011)An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)Circuits, Systems, and Signal Processing10.1007/s00034-010-9211-730:1(89-105)Online publication date: 1-Feb-2011
https://dl.acm.org/doi/10.1007/s00034-010-9211-7
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Clock-Gating in FPGAs: A Novel and Comparative Evaluation

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