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View all- Brenner USilvanus ASilvanus J(2022)Constructing depth-optimum circuits for adders and And-Or pathsDiscrete Applied Mathematics10.1016/j.dam.2021.12.007310(10-31)Online publication date: Mar-2022
Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Two
Article No.: 4, Pages 1 - 18
Abstract
We consider the problem of constructing fast and small binary adder circuits. Among widely used adders, the Kogge-Stone adder is often considered the fastest, because it computes the carry bits for two n-bit numbers (where n is a power of two) with a depth of 2 log2n logic gates, size 4 nlog2n, and all fan-outs bounded by two. Fan-outs of more than two are disadvantageous in practice, because they lead to the insertion of repeaters for repowering the signal and additional depth in the physical implementation.
However, the depth bound of the Kogge-Stone adder is off by a factor of two from the lower bound of log2n. Two separate constructions by Brent and Krapchenko achieve this lower bound asymptotically. Brent’s construction gives neither a bound on the fan-out nor the size, while Krapchenko’s adder has linear size, but can have up to linear fan-out. With a fan-out bound of two, neither construction achieves a depth of less than 2 log2n.
In a further approach, Brent and Kung proposed an adder with linear size and fan-out two but twice the depth of the Kogge-Stone adder.
These results are 33–43 years old and no substantial theoretical improvement for has been made since then. In this article, we integrate the individual advantages of all previous adder circuits into a new family of full adders, the first to improve on the depth bound of 2 log2n while maintaining a fan-out bound of two. Our adders achieve an asymptotically optimum logic gate depth of log2n + o(log 2n) and linear size O(n).
References
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Index Terms
- Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Two
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January 2018
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Publication History
Published: 14 December 2017
Accepted: 01 September 2017
Revised: 01 September 2017
Received: 01 January 2017
Published in TALG Volume 14, Issue 1
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View all- Brenner USilvanus ASilvanus J(2022)Constructing depth-optimum circuits for adders and And-Or pathsDiscrete Applied Mathematics10.1016/j.dam.2021.12.007310(10-31)Online publication date: Mar-2022
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