Marakkalage DDe Micheli G(2024)Fanout-Bounded Logic Synthesis for Emerging TechnologiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333944043:5(1415-1428)Online publication date: May-2024
https://doi.org/10.1109/TCAD.2023.3339440
Marakkalage DDe Micheli G(2023)Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137314(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137314
Guo LLau JChi YWang JYu CChen ZZhang ZCong J(2020)Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218718(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218718
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Index Terms

Bounding Fan-out in Logical Networks
1. Mathematics of computing
  1. Discrete mathematics
2. Theory of computation
  1. Models of computation

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Published In

Journal of the ACM Volume 31, Issue 1

Jan. 1984

188 pages

ISSN:0004-5411

EISSN:1557-735X

DOI:10.1145/2422

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 1984

Published in JACM Volume 31, Issue 1

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Marakkalage DDe Micheli G(2024)Fanout-Bounded Logic Synthesis for Emerging TechnologiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333944043:5(1415-1428)Online publication date: May-2024
https://doi.org/10.1109/TCAD.2023.3339440
Marakkalage DDe Micheli G(2023)Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137314(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137314
Guo LLau JChi YWang JYu CChen ZZhang ZCong J(2020)Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218718(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218718
Eslami FWilton S(2018)Rapid Triggering Capability Using an Adaptive Overlay during FPGA DebugACM Transactions on Design Automation of Electronic Systems10.1145/324104523:6(1-25)Online publication date: 6-Dec-2018
https://dl.acm.org/doi/10.1145/3241045
Ng HLiu SLuk WAnderson JBazargan K(2018)ADAMProceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3174243.3174247(189-198)Online publication date: 15-Feb-2018
https://dl.acm.org/doi/10.1145/3174243.3174247
Held SSpirkl S(2017)Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out TwoACM Transactions on Algorithms10.1145/314721514:1(1-18)Online publication date: 14-Dec-2017
https://dl.acm.org/doi/10.1145/3147215
Khatri SShenoy NGiomi JKhouja A(2016)Logic SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-4(27-55)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-4
Dershowitz NFalkovich-Derzhavetz E(2016)On the parallel computation thesisLogic Journal of IGPL10.1093/jigpal/jzw00824:3(346-374)Online publication date: 14-Mar-2016
https://doi.org/10.1093/jigpal/jzw008
Murgai R(2015)Technology-Dependent Logic OptimizationProceedings of the IEEE10.1109/JPROC.2015.2484299103:11(2004-2020)Online publication date: Nov-2015
https://doi.org/10.1109/JPROC.2015.2484299
DeHon A(2015)Fundamental Underpinnings of Reconfigurable Computing ArchitecturesProceedings of the IEEE10.1109/JPROC.2014.2387696103:3(355-378)Online publication date: Mar-2015
https://doi.org/10.1109/JPROC.2014.2387696
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Recurrent neural networks training with stable bounding ellipsoid algorithm

On limited fan-in optimal neural networks

Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints

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