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A Study of Cache Management Mechanisms for Real-Time Embedded Systems

Published: 21 September 2018 Publication History

Abstract

Due to the rapid development in the technology, embedded systems have an effective part in controlling and managing variety of hardware and software systems. These systems plan to solve problems that make embedded systems become more complex than before. The majority of embedded systems are currently intended to be more interactive with the environment and process data in real-time in order to fulfil requirements that recruited for. Thus, this requires a high speed of processing data to produce an output. Hence multicore processors are usually employed in embedded system design. To ensure that embedded systems as processing units work perfectly to finish a task with expecting the Worst-Case Execution Time (WCET). A considerable number of researches have been done to handle cache memory organization for multicore processor units in real-time embedded systems. To this end, this paper presents a study of cache management techniques in real-time embedded systems.

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Cited By

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  • (2020)A Dynamic Instruction Cache Locking Approach for Minimizing Worst Case Execution Time of a Single TaskIEEE Access10.1109/ACCESS.2020.30381708(208003-208015)Online publication date: 2020

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cover image ACM Other conferences
ISCSIC '18: Proceedings of the 2nd International Symposium on Computer Science and Intelligent Control
September 2018
363 pages
ISBN:9781450366281
DOI:10.1145/3284557
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 21 September 2018

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Author Tags

  1. Cache memory
  2. embedded systems
  3. processor
  4. real-time embedded systems
  5. replacement algorithms
  6. replacement polices

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  • Refereed limited

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ISCSIC '18

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ISCSIC '18 Paper Acceptance Rate 73 of 152 submissions, 48%;
Overall Acceptance Rate 192 of 401 submissions, 48%

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  • (2020)A Dynamic Instruction Cache Locking Approach for Minimizing Worst Case Execution Time of a Single TaskIEEE Access10.1109/ACCESS.2020.30381708(208003-208015)Online publication date: 2020

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