research-article

Predictable task migration for locked caches in multi-core systems

Authors:

Harini RamaprasadAuthors Info & Claims

LCTES '11: Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems

Pages 131 - 140

https://doi.org/10.1145/1967677.1967696

Published: 11 April 2011 Publication History

Abstract

Locking cache lines in hard real-time systems is a common means of achieving predictability of cache access behavior and tightening as well as reducing worst case execution time, especially in a multitasking environment. However, cache locking poses a challenge for multi-core hard real-time systems since theoretically optimal scheduling techniques on multi-core architectures assume zero cost for task migration. Tasks with locked cache lines need to proactively migrate these lines before the next invocation of the task. Otherwise, cache locking on multi-core architectures becomes useless as predictability is compromised.

This paper proposes hardware-based push-assisted cache migration as a means to retain locks on cache lines across migrations. We extend the push-assisted migration model with several cache migration techniques to efficiently retain locked cache lines on a bus-based chip multi-processor architecture. We also provide deterministic migration delay bounds that help the scheduler decide which migration technique(s) to utilize to relocate a single or multiple tasks. This information also allows the scheduler to determine feasibility of task migrations, which is critical for the safety of any hard real-time system. Such proactive migration of locked cache lines in multi-cores is unprecedented to our knowledge.

References

[1]

Hypertransport technology. http://www.hypertransport.org.

[2]

Tilera processor family. http://www.tilera.com/products/processors.php.

[3]

Wcet project benchmarks, 2007. http://www.mrtc.mdh.se/projects/-wcetbenchmarks.html.

[4]

A. Acquaviva, A. Alimonda, S. Carta, and M. Pittau. Assessing task migration impact on embedded soft real-time streaming multimedia applications. EURASIP J. Embedded Syst., 2008(2):1--15, 2008.

Digital Library

[5]

J. Anderson, J. Calandrino, and U. Devi. Real-time scheduling on multicore platforms. In IEEE Real-Time Embedded Technology and Applications Symposium, pages 179--190, April 2006.

Digital Library

[6]

J. Anderson and A. Srinivasan. Mixed pfair/erfair scheduling of asynchronous periodic tasks. In Euromicro Conference on Real-Time Systems, pages 76--85, June 2001.

Digital Library

[7]

S. Baruah. Techniques for multiprocessor global schedulability analysis. In IEEE Real-Time Systems Symposium, 2007.

Digital Library

[8]

S. Baruah, N. Cohen, C.G. Plaxton, and D. Varvel. Proportionate progress: A notion of fairness in resource allocation. Algorithmica, 15:600--625, 1996.

Digital Library

[9]

S. Bertozzi, A. Acquaviva, D. Bertozzi, and A. Poggiali. Supporting task migration in multi-processor systems-on-chip: a feasibility study. In Design, Automation and Test in Europe, pages 15--20, 2006.

Digital Library

[10]

J. Calandrino and J. Anderson. Cache-aware real-time scheduling on multicore platforms: Heuristics and a case study. In Euromicro Conference on Real-Time Systems, pages 209--308, July 2008.

Digital Library

[11]

D. Choffnes, M. Astley, and M. J. Ward. Migration policies for multicore fair-share scheduling. ACM SIGOPS Operating Systems Review, 42:92--93, 2008.

Digital Library

[12]

S.K. Dhall and C.L. Liu. On a real-time scheduling problem. Operations Research, 26(1):127--140, 1978.

Digital Library

[13]

Noel Eisley, Li-Shiuan Peh, and Li Shang. Leveraging on-chip networks for data cache migration in chip multiprocessors. In International conference on Parallel architectures and compilation techniques, pages 197--207, 2008.

Digital Library

[14]

D. Hardy and I. Puaut. Estimation of cache related migration delays for multi-core processors with shared instruction caches. In Proceedings of the 17th Real-Time and Network Systems, Paris, France, 2009.

[15]

T. Li, D. Baumberger, D. A. Koufaty, and S. Hahn. Efficient operating system scheduling for performance-asymmetric multi-core architectures. In International Conference on Supercomputing, pages 1--11, November 2007.

Digital Library

[16]

M. Moir and S. Ramamurthy. Pfair scheduling of fixed and migrating periodic tasks on multiple resources. In IEEE Real-Time Systems Symposium, pages 294--303, December 1999.

Digital Library

[17]

Isabelle Puaut. Wcet-centric software-controlled instruction caches for hard real-time systems. In Euromicro Conference on Real-Time Systems, pages 217--226, 2006.

Digital Library

[18]

Isabelle Puaut and David Decotigny. Low-complexity algorithms for static cache locking in multitasking hard real-time systems. In Real- Time Systems, pages 114--123, 2002.

Digital Library

[19]

Isabelle Puaut and Christophe Pais. Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison. In Design, Automation and Test in Europe, pages 1484--1489, San Jose, CA, USA, 2007. EDA Consortium.

Digital Library

[20]

H. Ramaprasad and F. Mueller. Tightening the bounds on feasible preemptions. Transactions on Embedded Computing Systems, 2008.

Digital Library

[21]

J. Rattner. Tera-scale research program. In Intel Dev. Forum, 2006.

[22]

J. Renau, B. Fragela, J. Tuck, W. Liu, L. Ceze, S. Sarangi, P. Sack, and and P. Montesinos K. Strauss. Sesc simulator. http://sesc.sourceforge.net, Jan. 2005.

[23]

A. Sarkar, F. Mueller, H. Ramaprasad, and S. Mohan. Push-assisted migration of real-time tasks in multi-core processors. In ACM SIGPLAN Conference on Language, Compiler, and Tool Support for Embedded Systems, pages 80--89, New York, NY, USA, 2009. ACM.

Digital Library

[24]

A. Srinivasan and J. Anderson. Optimal rate-based scheduling on multiprocessors. In ACM Symposium on Theory of Computing, pages 189--198, May 2002.

Digital Library

[25]

J. Staschulat, S. Schliecker, and R. Ernst. Scheduling analysis of realtime systems with precise modeling of cache related preemption delay. In Euromicro Conference on Real-Time Systems, pages 41--48, 2005.

Digital Library

[26]

Vivy Suhendra and Tulika Mitra. Exploring locking & partitioning for predictable shared caches on multi-cores. In Design Automation Conference, pages 300--303, New York, NY, USA, 2008. ACM.

Digital Library

[27]

X. Vera, B. Lisper, and J. Xue. Data caches in multitasking hard realtime systems. In IEEE Real-Time Systems Symposium, 2003.

Digital Library

[28]

E. Wandeler and L. Thiele. Optimal tdma time slot and cycle length allocation for hard real-time systems. In Proceedings of Asia and South Pacific Design Automation Conference, Yokohama, Japan, 2006.

Digital Library

Cited By

Lugo TLozano SFernandez JCarretero J(2022)A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore PlatformsIEEE Access10.1109/ACCESS.2022.315189110(21853-21882)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3151891
Roozkhosh SMancuso R(2020)The Potential of Programmable Logic in the Middle: Cache Bleaching2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS48715.2020.00006(296-309)Online publication date: Apr-2020
https://doi.org/10.1109/RTAS48715.2020.00006
Zhenyang LXiangdong LJun L(2020)Scheduling Parallel Real-Time Tasks for Multicore Systems2020 International Conference on Service Science (ICSS)10.1109/ICSS50103.2020.00024(102-106)Online publication date: Aug-2020
https://doi.org/10.1109/ICSS50103.2020.00024
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Index Terms

Predictable task migration for locked caches in multi-core systems

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cover image ACM Conferences

LCTES '11: Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems

April 2011

182 pages

ISBN:9781450305556

DOI:10.1145/1967677

General Chair:
Jan Vitek
Purdue University, USA
,
Program Chair:
Bjorn De Sutter
Ghent University, Belgium

ACM SIGPLAN Notices Volume 46, Issue 5
LCTES '10
May 2011
170 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/2016603
Issue’s Table of Contents

Copyright © 2011 ACM.

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Published: 11 April 2011

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LCTES '11

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LCTES '11: SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems

April 11 - 14, 2011

IL, Chicago, USA

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Overall Acceptance Rate 116 of 438 submissions, 26%

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Cited By

Lugo TLozano SFernandez JCarretero J(2022)A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore PlatformsIEEE Access10.1109/ACCESS.2022.315189110(21853-21882)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3151891
Roozkhosh SMancuso R(2020)The Potential of Programmable Logic in the Middle: Cache Bleaching2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS48715.2020.00006(296-309)Online publication date: Apr-2020
https://doi.org/10.1109/RTAS48715.2020.00006
Zhenyang LXiangdong LJun L(2020)Scheduling Parallel Real-Time Tasks for Multicore Systems2020 International Conference on Service Science (ICSS)10.1109/ICSS50103.2020.00024(102-106)Online publication date: Aug-2020
https://doi.org/10.1109/ICSS50103.2020.00024
Dohan MAgyeman M(2018)A Study of Cache Management Mechanisms for Real-Time Embedded SystemsProceedings of the 2nd International Symposium on Computer Science and Intelligent Control10.1145/3284557.3284559(1-5)Online publication date: 21-Sep-2018
https://dl.acm.org/doi/10.1145/3284557.3284559
Boudjadar JKim JNadjm-Tehrani STalpin J(2016)Performance-aware scheduling of multicore time-critical systemsProceedings of the 14th ACM-IEEE International Conference on Formal Methods and Models for System Design10.5555/3343414.3343429(105-114)Online publication date: 18-Nov-2016
https://dl.acm.org/doi/10.5555/3343414.3343429
Gracioli GFröhlich A(2016)On the Design and Evaluation of a Real-Time Operating System for Cache-Coherent Multicore ArchitecturesACM SIGOPS Operating Systems Review10.1145/2883591.288359449:2(2-16)Online publication date: 20-Jan-2016
https://dl.acm.org/doi/10.1145/2883591.2883594
Yao GPellizzoni RBak SYun HCaccamo M(2016)Global Real-Time Memory-Centric Scheduling for Multicore SystemsIEEE Transactions on Computers10.1109/TC.2015.250057265:9(2739-2751)Online publication date: 1-Sep-2016
https://dl.acm.org/doi/10.1109/TC.2015.2500572
Brandenburg BGul M(2016)Global Scheduling Not Required: Simple, Near-Optimal Multiprocessor Real-Time Scheduling with Semi-Partitioned Reservations2016 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS.2016.019(99-110)Online publication date: Nov-2016
https://doi.org/10.1109/RTSS.2016.019
Boudjadar JKim JNadjm-Tehrani S(2016)Performance-aware scheduling of multicore time-critical systems2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)10.1109/MEMCOD.2016.7797753(105-114)Online publication date: Nov-2016
https://doi.org/10.1109/MEMCOD.2016.7797753
Gracioli GAlhammad AMancuso RFröhlich APellizzoni R(2015)A Survey on Cache Management Mechanisms for Real-Time Embedded SystemsACM Computing Surveys10.1145/283055548:2(1-36)Online publication date: 3-Nov-2015
https://dl.acm.org/doi/10.1145/2830555
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