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Programmable memory blocks supporting content-addressable memory

Authors:

Frank Heile,

Andrew Leaver, and

Kerry VeenstraAuthors Info & Claims

FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

February 2000

Pages 13 - 21

https://doi.org/10.1145/329166.329173

Published: 01 February 2000 Publication History

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Abstract

The Embedded System Block (ESB) of the APEX E programmable logic device family from Altera Corporation includes the capability of implementing content addressable memory (CAM) as well as product term macrocells, ROM, and dual port RAM. In CAM mode each ESB can implement a 32 word CAM with 32 bits per word. In product term mode, each ESB has 16 macrocells built out of 32 product terms with 32 literal inputs. The ability to reconfigure memory blocks in this way represents a new and innovative use of resources in a programmable logic device, requiring creative solutions in both the hardware and software domains. The architecture and features of this Embedded System Block are described.

References

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Altera Corporation, "APEX 20K Programmable Logic Device Family, Data Sheer', 1999.

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S. Wilton, J. Rose and Z. Vranesic, "Memory-to- Memory Connection Structures in FPGAs with Embedded Memory Arrays." Proceedings of the 5th International Symposium on FPGAs, FPGA 97, Feb 1997. (Submitted to 1EEE Trans. VLSI).

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S. Wilton, J. Rose and Z. Vranesic, " Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory Arrays," in CICC 96, the IEEE Custom Integrated Circuits Conf., San Diego, CA, May 1996, pp. 144-147.

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F. Heile, A. Leaver, "Hybrid Product Term and LUT Based Architecture Using Embedded Memory Blocks", Prec. ACM 7th International Symposium on FPGAs, FPGA 99, Monterey, CA., Feb. 1999.

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Cited By

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Amagasaki MShibata Y(2018)FPGA StructurePrinciples and Structures of FPGAs10.1007/978-981-13-0824-6_3(47-86)Online publication date: 4-Sep-2018
https://doi.org/10.1007/978-981-13-0824-6_3
Abdelhadi ALemieux G(2015)Modular SRAM-Based Binary Content-Addressable MemoriesProceedings of the 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2015.69(207-214)Online publication date: 2-May-2015
https://dl.acm.org/doi/10.1109/FCCM.2015.69
Abdelhadi ALemieux G(2014)Deep and narrow binary content-addressable memories using FPGA-based BRAMs2014 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2014.7082808(318-321)Online publication date: Dec-2014
https://doi.org/10.1109/FPT.2014.7082808
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Index Terms

Programmable memory blocks supporting content-addressable memory
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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Information

Published In

FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

February 2000

223 pages

ISBN:1581131933

DOI:10.1145/329166

Chairmen:
Steve Trimberger
Xilinx, San Jose, CA
,
Scott Hauck
Univ. of Washington, Seattle

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 February 2000

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FPGA00

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SIGDA

FPGA00: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 10 - 11, 2000

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

View all

Amagasaki MShibata Y(2018)FPGA StructurePrinciples and Structures of FPGAs10.1007/978-981-13-0824-6_3(47-86)Online publication date: 4-Sep-2018
https://doi.org/10.1007/978-981-13-0824-6_3
Abdelhadi ALemieux G(2015)Modular SRAM-Based Binary Content-Addressable MemoriesProceedings of the 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2015.69(207-214)Online publication date: 2-May-2015
https://dl.acm.org/doi/10.1109/FCCM.2015.69
Abdelhadi ALemieux G(2014)Deep and narrow binary content-addressable memories using FPGA-based BRAMs2014 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2014.7082808(318-321)Online publication date: Dec-2014
https://doi.org/10.1109/FPT.2014.7082808
Zerbini CFinochietto J(2012)Performance evaluation of packet classification on FPGA-based TCAM emulation architectures2012 IEEE Global Communications Conference (GLOBECOM)10.1109/GLOCOM.2012.6503535(2766-2771)Online publication date: Dec-2012
https://doi.org/10.1109/GLOCOM.2012.6503535
McLaughlin KO'Connor NSezer S(2006)Exploring CAM Design For Network Processing Using FPGA TechnologyAdvanced Int'l Conference on Telecommunications and Int'l Conference on Internet and Web Applications and Services (AICT-ICIW'06)10.1109/AICT-ICIW.2006.96(84-84)Online publication date: 2006
https://doi.org/10.1109/AICT-ICIW.2006.96
Mai KHo RAlon ELiu DYounggon Kim Patil DHorowitz M(2005)Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-/spl mu/m CMOSIEEE Journal of Solid-State Circuits10.1109/JSSC.2004.83799240:1(261-275)Online publication date: Jan-2005
https://doi.org/10.1109/JSSC.2004.837992
Hutton MChan VKazarian PMaruri VNgai TPark JPatel RPedersen BSchleicher JShumarayev SSchlag MTrimberger S(2002)Interconnect enhancements for a high-speed PLD architectureProceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays10.1145/503048.503050(3-10)Online publication date: 24-Feb-2002
https://dl.acm.org/doi/10.1145/503048.503050

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