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Evaluation of Hardware Data Prefetchers on Server Processors

Published: 18 June 2019 Publication History

Abstract

Data prefetching, i.e., the act of predicting an application’s future memory accesses and fetching those that are not in the on-chip caches, is a well-known and widely used approach to hide the long latency of memory accesses. The fruitfulness of data prefetching is evident to both industry and academy: Nowadays, almost every high-performance processor incorporates a few data prefetchers for capturing various access patterns of applications; besides, there is a myriad of proposals for data prefetching in the research literature, where each proposal enhances the efficiency of prefetching in a specific way.
In this survey, we evaluate the effectiveness of data prefetching in the context of server applications and shed light on its design trade-offs. To do so, we choose a target architecture based on a contemporary server processor and stack various state-of-the-art data prefetchers on top of it. We analyze the prefetchers in terms of their ability to predict memory accesses and enhance overall system performance, as well as their imposed overheads. Finally, by comparing the state-of-the-art prefetchers with impractical ideal prefetchers, we motivate further work on improving data prefetching techniques.

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cover image ACM Computing Surveys
ACM Computing Surveys  Volume 52, Issue 3
May 2020
734 pages
ISSN:0360-0300
EISSN:1557-7341
DOI:10.1145/3341324
  • Editor:
  • Sartaj Sahni
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 18 June 2019
Accepted: 01 February 2019
Revised: 01 December 2018
Received: 01 August 2017
Published in CSUR Volume 52, Issue 3

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Author Tags

  1. Data prefetching
  2. and spatio-temporal correlation
  3. scale-out workloads
  4. server processors

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  • Refereed

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  • Iran National Science Foundation (INSF)

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  • (2022)BIOS-Based Server Intelligent OptimizationSensors10.3390/s2218673022:18(6730)Online publication date: 6-Sep-2022
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