research-article

A First ISA-Level Characterization of EM Pulse Effects on Superscalar Microarchitectures: A Secure Software Perspective

Authors:

Karine Heydemann,

Alexandre Berzati,

Fabien Majéric,

Albert CohenAuthors Info & Claims

ARES '19: Proceedings of the 14th International Conference on Availability, Reliability and Security

Article No.: 7, Pages 1 - 10

https://doi.org/10.1145/3339252.3339253

Published: 26 August 2019 Publication History

Abstract

In the area of physical attacks, system-on-chip (SoC) designs have not received the same level of attention as simpler micro-controllers. We try to model the behavior of secure software running on a superscalar out-of-order microprocessor typical of more complex SoC, in the presence of electromagnetic (EM) pulses. We first show that it is possible, in a black box approach, to corrupt the loop iteration count of both original and hardened versions of two sensitive loops. We propose a characterization methodology based on very simple codes, to understand and classify the fault effects at the level of the instruction set architecture (ISA). The resulting classification includes the well established instruction skip and register corruption models, as well as new effects specific to more complex processors, such as operand substitution, multiple correlated register corruptions, advanced control-flow hijacking, and combinations of all reported effects. This diversity and complexity of effects can lead to powerful attacks. The proposed methodology and fault classification at ISA level is a first step towards a more complete characterization. It is also a tool supporting the designers of software and hardware countermeasures.

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Cited By

Alshaer IAl-Kaf AEgloff VBeroulle V(2024)Modeling Clock Glitch Fault Injection Effects on a RISC-V Microcontroller2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS60994.2024.10616064(1-3)Online publication date: 3-Jul-2024
https://doi.org/10.1109/IOLTS60994.2024.10616064
Fanjas CAboulkassimi DPontié SClédière J(2024)PoP DRAM: A new EMFI approach based on EM-induced glitches on SoC2024 Workshop on Fault Detection and Tolerance in Cryptography (FDTC)10.1109/FDTC64268.2024.00010(10-21)Online publication date: 4-Sep-2024
https://doi.org/10.1109/FDTC64268.2024.00010
Alshaer IAl-kaf AEgloff VBeroulle V(2024)Inferred Fault Models for RISC-V and Arm: A Comparative Study2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT63277.2024.10753562(1-6)Online publication date: 8-Oct-2024
https://doi.org/10.1109/DFT63277.2024.10753562
Show More Cited By

Index Terms

A First ISA-Level Characterization of EM Pulse Effects on Superscalar Microarchitectures: A Secure Software Perspective
1. Computer systems organization
  1. Embedded and cyber-physical systems
2. Security and privacy
  1. Security in hardware
    1. Hardware attacks and countermeasures
  2. Software and application security

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cover image ACM Other conferences

ARES '19: Proceedings of the 14th International Conference on Availability, Reliability and Security

August 2019

979 pages

ISBN:9781450371643

DOI:10.1145/3339252

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 26 August 2019

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ARES '19

ARES '19: 14th International Conference on Availability, Reliability and Security

August 26 - 29, 2019

CA, Canterbury, United Kingdom

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Overall Acceptance Rate 228 of 451 submissions, 51%

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Cited By

Alshaer IAl-Kaf AEgloff VBeroulle V(2024)Modeling Clock Glitch Fault Injection Effects on a RISC-V Microcontroller2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS60994.2024.10616064(1-3)Online publication date: 3-Jul-2024
https://doi.org/10.1109/IOLTS60994.2024.10616064
Fanjas CAboulkassimi DPontié SClédière J(2024)PoP DRAM: A new EMFI approach based on EM-induced glitches on SoC2024 Workshop on Fault Detection and Tolerance in Cryptography (FDTC)10.1109/FDTC64268.2024.00010(10-21)Online publication date: 4-Sep-2024
https://doi.org/10.1109/FDTC64268.2024.00010
Alshaer IAl-kaf AEgloff VBeroulle V(2024)Inferred Fault Models for RISC-V and Arm: A Comparative Study2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT63277.2024.10753562(1-6)Online publication date: 8-Oct-2024
https://doi.org/10.1109/DFT63277.2024.10753562
Alshaer IBurghoorn GColombier BDeleuze CBeroulle VMaistri P(2024)Cross-layer analysis of clock glitch fault injection while fetching variable-length instructionsJournal of Cryptographic Engineering10.1007/s13389-024-00352-614:2(325-342)Online publication date: 23-Apr-2024
https://doi.org/10.1007/s13389-024-00352-6
Alshaer IColombier BDeleuze CBeroulle VMaistri P(2024)Microarchitectural Insights into Unexplained Behaviors Under Clock Glitch Fault InjectionSmart Card Research and Advanced Applications10.1007/978-3-031-54409-5_1(3-22)Online publication date: 23-Feb-2024
https://doi.org/10.1007/978-3-031-54409-5_1
Carta DZaccaria VQuagliarella GMolteni M(2023)Efficient Attack-Surface Exploration for Electromagnetic Fault InjectionConstructive Side-Channel Analysis and Secure Design10.1007/978-3-031-29497-6_2(23-41)Online publication date: 23-Mar-2023
https://doi.org/10.1007/978-3-031-29497-6_2
Gicquel AHardy DHeydemann KRohou E(2023)SAMVA: Static Analysis for Multi-fault Attack Paths DeterminationConstructive Side-Channel Analysis and Secure Design10.1007/978-3-031-29497-6_1(3-22)Online publication date: 23-Mar-2023
https://doi.org/10.1007/978-3-031-29497-6_1
Farahmandi FRahman MRajendran STehranipoor MFarahmandi FRahman MRajendran STehranipoor M(2023)CAD for Electromagnetic Fault InjectionCAD for Hardware Security10.1007/978-3-031-26896-0_8(169-185)Online publication date: 28-Jan-2023
https://doi.org/10.1007/978-3-031-26896-0_8
Tollec SAsavoae MCourousse DHeydemann KJan M(2022)Exploration of Fault Effects on Formal RISC-V Microarchitecture Models2022 Workshop on Fault Detection and Tolerance in Cryptography (FDTC)10.1109/FDTC57191.2022.00017(73-83)Online publication date: Sep-2022
https://doi.org/10.1109/FDTC57191.2022.00017
Alshaer IColombier BDeleuze CBeroulle VMaistri P(2022)Variable-Length Instruction Set: Feature or Bug?2022 25th Euromicro Conference on Digital System Design (DSD)10.1109/DSD57027.2022.00068(464-471)Online publication date: Aug-2022
https://doi.org/10.1109/DSD57027.2022.00068
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