Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/337292.337569acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article
Free access

Singularity-treated quadrature-evaluated method of moments solver for 3-D capacitance extraction

Published: 02 June 2019 Publication History

Abstract

While research work on fast integral equation solver has resulted in several algorithms of similar linear equation solving performance, it has been well observed that the convergence of capacitance versus discretization is rather slow due to the most commonly used first-order collocation or Galerkin methods. This paper reports a new high-order scheme, Quadrature-evaluated Method of Moments Solver (QMMS), that uses high-order weighting and Gaussian quadrature to optimally handle the singularities at the edges and corners. For practical interconnect extraction problems, singularities at edges are analytically known and the corresponding Gaussian nodes allocation affords a near optimal discretization scheme. The new formulation avoids the special position-dependent quadrature rules, and surprisingly, provides a well-behaved matrix that converges rapidly without any pre-conditioning. Combining the high-order scheme with a kernel-independent fast solver yields an efficient algorithm for 3-D capacitance extraction.

References

[1]
R.F. Harrington. Field computation by moment methods. New York: Macmillan, 1968.
[2]
J.D. Jackson. Classical electrodynamics. Wiley, New York, 3rd ed. edition, 1999.
[3]
S. Kapur and d. Long. IES&3: A fast integral equation solver for efficient 3-dimensional extractions. In 37th International Conference on Computer Aided Design, Nov 1997.
[4]
S.Kapur and D. Long. High-order Nystrom schemes for efficient 3-d capacitance extraction. In IEEE/ACM INternational Conference on Computer-Aided Design, pages 178-85, San Jose, CA, Nov. 1998. New York, NY, USA: ACM.
[5]
W.Sun, W. Wei-Ming Dai, and W. Hong. Fast parameter extraction of general interconnects using geometry independent measured equation of invariance. IEEE Transactions on Microwave Theory and Techniques, 45(5):827-36, May 1997.
[6]
J.Tausch and J. White. A multiscale method for fast capacitance extraction. In Design and Automation Conference, pages 537-542, New Orleans, June 1999. New York, NY, USA: IEEE.
[7]
J. Zhao, W. Dai, S. Kapur, and D. Long. Efficient three-dimensional extraction based on static and full-wave layered green's functions. In Design and Automation Conference, pages 224-9, San Francisco, June 1998. New York, NY, USA: IEEE.

Cited By

View all
  • (2006)Compact modeling and fast simulation of on-chip interconnect linesIEEE Transactions on Magnetics10.1109/TMAG.2006.87146642:4(547-550)Online publication date: Apr-2006

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
DAC '00: Proceedings of the 37th Annual Design Automation Conference
June 2000
819 pages
ISBN:1581131879
DOI:10.1145/337292
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2019

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Article

Conference

DAC00
Sponsor:
DAC00: ACM/IEEE-CAS/EDAC Design Automation Conference
June 5 - 9, 2000
California, Los Angeles, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25
62nd ACM/IEEE Design Automation Conference
June 22 - 26, 2025
San Francisco , CA , USA

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)22
  • Downloads (Last 6 weeks)7
Reflects downloads up to 08 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2006)Compact modeling and fast simulation of on-chip interconnect linesIEEE Transactions on Magnetics10.1109/TMAG.2006.87146642:4(547-550)Online publication date: Apr-2006

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media