research-article

A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators

Authors:

Christian Maximilian Karle,

Marius Kreutzer,

Johannes Pfau,

Jürgen BeckerAuthors Info & Claims

HEART '22: Proceedings of the 12th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies

Pages 33 - 41

https://doi.org/10.1145/3535044.3535049

Published: 09 June 2022 Publication History

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Abstract

The novel communication 6G requires raw data rates of up to 400 Gbit s− 1 in a single Field Programmable Gate Array (FPGA) front-end. For these high data rates, a Software Defined Radio (SDR) on a multi-core processor reaches a performance limit due to technical boundaries, clock speeds and overhead in multiprocessing. Hence, additional hardware accelerators based on Application Specific Integrated Circuits (ASICs) or FPGAs are required to process those large amounts of data. In this paper, our hardware/software co-design concept is presented, which allows for the integration of hardware accelerators realized in FPGAs, to improve overall system performance. We can access the accelerators from the widely used GNU Radio, which also allows non-FPGA user to benefit from the acceleration. For this purpose, a concept to share data between Processing System (PS) and Programmable Logic (PL) is developed and evaluated regarding its suitability for high bandwidth applications. Using a common application for evaluation, we are able to compare a hardware/software co-design with an entirely software-based implementation. Resulting in an overall performance increase by a factor of up to 4.5, while serving as a foundation for an easy-to-use method for hardware accelerators in GNU Radio.

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Cited By

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Karle CNeu MNuss BChen JWitte LScheder AHarbaum TBecker J(2024)Modular Hardware Design for High-Performance MIMO-Capable SDR Systems to Accelerate 6G Development2024 IEEE 37th International System-on-Chip Conference (SOCC)10.1109/SOCC62300.2024.10737765(1-6)Online publication date: 16-Sep-2024
https://doi.org/10.1109/SOCC62300.2024.10737765
Neu MBecker JDorwarth PFerber TReuter LStefkova SUnger K(2024)Real-Time Graph Building on FPGAs for Machine Learning Trigger Applications in Particle PhysicsComputing and Software for Big Science10.1007/s41781-024-00117-08:1Online publication date: 21-Mar-2024
https://doi.org/10.1007/s41781-024-00117-0
Polese MDohler MDressler FErol-Kantarci MJana RKnopp RMelodia T(2023)Empowering the 6G Cellular Architecture With Open RANIEEE Journal on Selected Areas in Communications10.1109/JSAC.2023.333461042:2(245-262)Online publication date: 28-Nov-2023
https://dl.acm.org/doi/10.1109/JSAC.2023.3334610
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HEART '22: Proceedings of the 12th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies

June 2022

114 pages

ISBN:9781450396608

DOI:10.1145/3535044

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

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Published: 09 June 2022

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Federal Ministry of Education and Research of Germany

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HEART2022

HEART2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies

June 9 - 10, 2022

Tsukuba, Japan

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HEART '22 Paper Acceptance Rate 10 of 21 submissions, 48%;

Overall Acceptance Rate 22 of 50 submissions, 44%

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Karle CNeu MNuss BChen JWitte LScheder AHarbaum TBecker J(2024)Modular Hardware Design for High-Performance MIMO-Capable SDR Systems to Accelerate 6G Development2024 IEEE 37th International System-on-Chip Conference (SOCC)10.1109/SOCC62300.2024.10737765(1-6)Online publication date: 16-Sep-2024
https://doi.org/10.1109/SOCC62300.2024.10737765
Neu MBecker JDorwarth PFerber TReuter LStefkova SUnger K(2024)Real-Time Graph Building on FPGAs for Machine Learning Trigger Applications in Particle PhysicsComputing and Software for Big Science10.1007/s41781-024-00117-08:1Online publication date: 21-Mar-2024
https://doi.org/10.1007/s41781-024-00117-0
Polese MDohler MDressler FErol-Kantarci MJana RKnopp RMelodia T(2023)Empowering the 6G Cellular Architecture With Open RANIEEE Journal on Selected Areas in Communications10.1109/JSAC.2023.333461042:2(245-262)Online publication date: 28-Nov-2023
https://dl.acm.org/doi/10.1109/JSAC.2023.3334610
Neu MKarle CNuss BGroeschel PBecker J(2023)A Scalable and Cost-Efficient Antenna Testbed Using FPGA-Server Compound Structures for Prototyping 6G Applications2023 19th International Conference on Distributed Computing in Smart Systems and the Internet of Things (DCOSS-IoT)10.1109/DCOSS-IoT58021.2023.00039(171-178)Online publication date: Jun-2023
https://doi.org/10.1109/DCOSS-IoT58021.2023.00039
Havinga TJiao XAslam MLiu WMoerman I(2023)Improved TDD operation on Software-Defined Radio platforms towards future wireless standardsComputer Communications10.1016/j.comcom.2023.06.026209:C(178-187)Online publication date: 1-Sep-2023
https://dl.acm.org/doi/10.1016/j.comcom.2023.06.026

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Design and evaluation of a hardware/software FPGA-based system for fast image processing

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