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T-TER: Defeating A2 Trojans with Targeted Tamper-Evident Routing

Published: 10 July 2023 Publication History

Abstract

Since the inception of the Integrated Circuit (IC), the size of the transistors used to construct them has continually shrunk. While this advancement significantly improves computing capability, fabrication costs have skyrocketed. As a result, most IC designers must now outsource fabrication. Outsourcing, however, presents a security threat: comprehensive post-fabrication inspection is infeasible given the size of modern ICs, so it is nearly impossible to know if the foundry has altered the original design during fabrication (i.e., inserted a hardware Trojan). Defending against a foundry-side adversary is challenging because—even with as few as two gates—hardware Trojans can completely undermine software security. Researchers have attempted to both detect and prevent foundry-side attacks, but all existing defenses are ineffective against additive Trojans with footprints of a few gates or less.
We present Targeted Tamper-Evident Routing (T-TER), a layout-level defense against untrusted foundries, capable of thwarting the insertion of even the stealthiest hardware Trojans. T-TER is directed and routing-centric: it prevents foundry-side attackers from routing Trojan wires to, or directly adjacent to, security-critical wires by shielding them with guard wires. Unlike shield wires commonly deployed for cross-talk reduction, T-TER guard wires pose an additional technical challenge: they must be tamper-evident in both the digital (deletion attacks) and analog (move and jog attacks) domains. We address this challenge by developing a class of designed-in guard wires that are added to the design specifically to protect security-critical wires. T-TER’s guard wires incur minimal overhead, scale with design complexity, and provide tamper-evidence against attacks. We implement automated tools (on top of commercial CAD tools) for deploying guard wires around targeted nets within an open-source System-on-Chip. Lastly, using an existing IC threat assessment toolchain, we show T-TER defeats even the stealthiest known hardware Trojan, with ≈  1% overhead.

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  • (2024)Detour-RS: Reroute Attack Vulnerability Assessment with Awareness of the Layout and ResourceCryptography10.3390/cryptography80200138:2(13)Online publication date: 6-Apr-2024

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cover image ACM Conferences
ASIA CCS '23: Proceedings of the 2023 ACM Asia Conference on Computer and Communications Security
July 2023
1066 pages
ISBN:9798400700989
DOI:10.1145/3579856
Publication rights licensed to ACM. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of the United States government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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Published: 10 July 2023

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Author Tags

  1. Fabrication-time Attacks and Defenses
  2. Hardware Security
  3. VLSI

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  • (2024)Detour-RS: Reroute Attack Vulnerability Assessment with Awareness of the Layout and ResourceCryptography10.3390/cryptography80200138:2(13)Online publication date: 6-Apr-2024

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