research-article

Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration

Authors:

Georgios Zacharopoulos,

Muhammad Huzaifa,

David BrooksAuthors Info & Claims

ACM Transactions on Embedded Computing Systems, Volume 22, Issue 3

Article No.: 53, Pages 1 - 23

https://doi.org/10.1145/3580394

Published: 20 April 2023 Publication History

Abstract

The design of heterogeneous systems that include domain specific accelerators is a challenging and time-consuming process. While taking into account area constraints, designers must decide which parts of an application to accelerate in hardware and which to leave in software. Moreover, applications in domains such as Extended Reality (XR) offer opportunities for various forms of parallel execution, including loop level, task level, and pipeline parallelism. To assist the design process and expose every possible level of parallelism, we present Trireme, a fully automated tool-chain that explores multiple levels of parallelism and produces domain-specific accelerator designs and configurations that maximize performance, given an area budget. FPGA SoCs were used as target platforms, and Catapult HLS [7] was used to synthesize RTL using a commercial 12 nm FinFET technology. Experiments on demanding benchmarks from the XR domain revealed a speedup of up to 20×, as well as a speedup of up to 37× for smaller applications, compared to software-only implementations.

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Cited By

Abdollahi MYeganli SBaharloo MBaniasadi A(2024)Hardware Design and Verification with Large Language Models: A Scoping Review, Challenges, and Open IssuesElectronics10.3390/electronics1401012014:1(120)Online publication date: 30-Dec-2024
https://doi.org/10.3390/electronics14010120
Gorgin SKarvandi MMoghari SFallah MLee J(2024)A Hardware Realization Framework for Fuzzy Inference System OptimizationElectronics10.3390/electronics1304069013:4(690)Online publication date: 8-Feb-2024
https://doi.org/10.3390/electronics13040690
Chang LGener SMack JSuluhan HAkoglu AChakrabarti C(2024)Coarse-Grained Task Parallelization by Dynamic Profiling for Heterogeneous SoC-Based Embedded SystemACM Transactions on Embedded Computing Systems10.1145/370463524:1(1-32)Online publication date: 15-Nov-2024
https://dl.acm.org/doi/10.1145/3704635
Show More Cited By

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Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 22, Issue 3

May 2023

519 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3592782

Editor:
Tulika Mitra
National University of Singapore, Singapore

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 20 April 2023

Online AM: 17 January 2023

Accepted: 09 January 2023

Revised: 11 November 2022

Received: 06 October 2021

Published in TECS Volume 22, Issue 3

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Software Analysis for Heterogeneous Computing Architectures
Swiss National Science Foundation (SNSF), by the National Science Foundation (US)
NSF
DARPA through the Domain-Specific System on Chip (DSSoC)
Applications Driving Architectures (ADA) Research Center

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Cited By

Abdollahi MYeganli SBaharloo MBaniasadi A(2024)Hardware Design and Verification with Large Language Models: A Scoping Review, Challenges, and Open IssuesElectronics10.3390/electronics1401012014:1(120)Online publication date: 30-Dec-2024
https://doi.org/10.3390/electronics14010120
Gorgin SKarvandi MMoghari SFallah MLee J(2024)A Hardware Realization Framework for Fuzzy Inference System OptimizationElectronics10.3390/electronics1304069013:4(690)Online publication date: 8-Feb-2024
https://doi.org/10.3390/electronics13040690
Chang LGener SMack JSuluhan HAkoglu AChakrabarti C(2024)Coarse-Grained Task Parallelization by Dynamic Profiling for Heterogeneous SoC-Based Embedded SystemACM Transactions on Embedded Computing Systems10.1145/370463524:1(1-32)Online publication date: 15-Nov-2024
https://dl.acm.org/doi/10.1145/3704635
Hussein EWaschneck BMayr C(2024)Automating application-driven customization of ASIPsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2024.103080148:COnline publication date: 2-Jul-2024
https://dl.acm.org/doi/10.1016/j.sysarc.2024.103080

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