Special Issue: “Approximation at the Edge”

The upcoming years will prioritize energy efficiency as the most crucial factor. Projections indicate that by 2040, the electricity demand for IT systems will surpass the capacity of global energy resources. Even before that, by 2025, data centers alone will consume a staggering 20% of the available electricity supply. This trend is also evident in the communications field, where the energy consumption of mobile broadband networks and mobile devices rivals that of data centers. Additionally, the Internet of Things (IoT) will soon connect approximately 50 billion devices to the cloud through wireless networks, further exacerbating these energy challenges.

Given this scenario, the concept of Approximate Computing (AxC) can significantly mitigate power requirements and reduce the energy footprint of computational tasks [1]. Nearly a decade ago, Approximate Computing emerged with the promise of achieving substantial overhead reduction (including energy, area, and latency) while accepting a minor sacrifice in computation accuracy within computing systems.

Naturally, new approaches have emerged to process data at its source or storage, such as in-memory and near-memory computing techniques. Similarly, techniques for data filtering at the edge (e.g., sensors, storage) are crucial for reducing communication network bandwidth. However, due to the limited resources and computational power of edge devices, approximate computing techniques often enable data acquisition, filtering, and reduction at the edge. In line with these observations and applications, there has been a growing interest in developing ultra-lightweight implementations of machine learning techniques specifically for edge computing.

This special issue aims to collect original manuscripts that explore techniques, architectures, and applications that highlight the intersection of edge computing and approximate computing. Researchers investigated how approximate computing techniques can enable or support edge computing, providing innovative solutions to address the associated challenges and harness the potential of this emerging field.

The call for papers attracted 12 submissions, and after a rigorous review, 6 papers have been accepted for this special issue. A brief summary of papers in this special issue is presented in the following:

In the article “Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAMs ”, the authors introduced a new method for generating memory-efficient table-based function approximation circuits, specifically targeting edge devices and FPGA platforms. Instead of using the conventional approach of equidistant sampling in the given interval with breakpoints and linear interpolation, the authors propose and compare three algorithms for dividing the interval into sub-intervals. This division significantly reduces the memory footprint by exploiting the observation that sub-intervals with low gradients can be sampled coarsely while guaranteeing the maximum interpolation error bound. Experiments on basic mathematical functions demonstrate substantial memory savings achieved through this technique. Moreover, they also introduced a hardware architecture that enables sub-interval selection, breakpoint lookup, and interpolation, all accomplished within a latency of only nine clock cycles. Furthermore, for each circuit design generated, we automatically instantiate Block RAMs (BRAMs) instead of synthesizing the reduced footprint function table using LookUp Table (LUT) primitives. This approach provides an additional level of resource efficiency.

In the article “AQuA: A New Image Quality Metric for Optimizing Video Analytics Systems ”, the authors proposed AQuA, a solution designed to safeguard application accuracy by evaluating the level of distortion in frames coming from cameras deployed at the edge. Indeed, such frames often suffer from distortions caused by factors such as lighting issues, sensor noise, and compression. These distortions not only degrade the visual quality but also impact the accuracy of deep learning applications that rely on these video streams. AQuA focuses on the analytical quality of frames rather than visual quality. It achieves this by training a novel metric called the classifier opinion score, using a lightweight, CNN-based feature extractor that is independent of specific objects. By accurately assessing the distortion levels of frames, AQuA demonstrates its applicability across multiple deep-learning applications. When employed to filter out poor-quality frames at the edge, it effectively reduces high-confidence errors in analytics applications by 17%. Furthermore, AQuA’s low overhead of just 14ms enables it to decrease computation time and average bandwidth usage by 25%.

The article “AutomaticGenerationofResourceandAccuracyConfigurableProcessingElements ” proposes a framework for automatically generating processing elements (PEs) that are configurable at synthesis time, specifically for two kernels: Generic Matrix Multiplication-Addition (GEMMA) and convolution operations. The authors conducted a design exploration by varying parameters such as data bit-width, operand sizes, and kernel sizes. For the GEMMA kernel, a tradeoff is observed between granularity and efficiency. Larger PEs with shorter data widths showed higher design efficiency, achieving a theoretical performance of up to 75 GMAC/s on a Xilinx XC7Z020 FPGA running at 100 MHz, with an efficiency of 27%. For the convolution operations kernel, the authors implemented two algorithms: window-based spatial convolution and Winograd. The former exhibits superior performance, achieving a rate of 150 GMAC/s with an efficiency of up to 47%. Winograd also outperforms spatial convolution in numerical evaluations, particularly when using a 3 \(\times\) 3 kernel filter. It shows a mean error of 11.01% with 4-bit operands and a PSNR of 16.28 dB, while spatial convolution exhibits a mean error of 38.2% and a PSNR of 5.89 dB. The developed PEs in this research serve as a foundation for further exploration in granular approximate accelerator research.

The article “Towards Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs ” introduces a novel carry-aware approximate radix-4 Booth multiplier design for SRAM-based FPGAs used in signal processing, image processing, and machine learning applications. The focus of the design is on addressing the challenges associated with carry-propagation when employing the widely used truncation of lower bits as an approximation technique. The proposed multiplier takes advantage of the built-in slice LUT and carry-chain resources in a unique configuration, simplifying the computation of upper and lower bits. This approach offers several significant benefits compared to the latest state-of-the-art designs.

The article “Energy-efficient Approximate Edge Inference Systems ” introduces AxIS, an approximate edge inference system for energy-efficient inference on edge devices. It proposes a systematic methodology for joint approximations across different subsystems in a DNN-based edge inference system, resulting in significant energy savings compared to approximating subsystems individually. In particular, the authors show how the sensor, memory, compute, and communication subsystems can all be approximated synergistically. Two variants of a smart camera system are considered: CamEdge, where the DNN is executed locally on the edge device, and CamCloud, where the edge device sends the captured image to a remote cloud server for DNN execution. Experimental results using a smart camera system demonstrate energy savings of 1.6\(\times\) to 4.7\(\times\) for large DNNs and 1.5\(\times\) to 3.6\(\times\) for small DNNs, with minimal quality loss. AxIS achieves 1.05\(\times\) to 3.25\(\times\) energy savings for image classification and 1.35\(\times\) to 4.2\(\times\) for object detection, outperforming isolated subsystem approximations. This approach shows promise for energy-efficient inference on edge devices.

Finally, in “A Methodology for Fault-tolerant Pareto-optimal Approximate Designs of FPGA-based Accelerators ”, the authors introduce a Design Space Exploration (DSE) methodology for applying Approximate Computing Techniques (ACTs) to FPGA-based accelerators in critical Edge computing systems. The methodology aims to find optimal design architectures that balance precision, area, power, performance, and reliability. By selectively implementing approximate circuits and applying mitigation techniques, significant gains in area, frequency, and power consumption are achieved without compromising output quality and system dependability. The evaluation of FPGA accelerators, including a JPEG encoder and an H.264/AVC decoder, demonstrates the effectiveness of the proposed methodology in improving performance and efficiency compared to traditional approaches.

In closing, the guest editors would like to thank all the authors, who significantly contributed to this SI, and the reviewers for their efforts in respecting deadlines and their constructive reviews. We are also grateful to the Editor-in-Chief, Tulika Mitra, for her support and to the ACM Transactions on Embedded Computing Systems publication staff as well, who collaborated with us at every step. We hope this SI will inspire further research and development ideas for applying approximate computing techniques at the edge.