Article

The sun fireplane system interconnect

Author:

Alan CharlesworthAuthors Info & Claims

SC '01: Proceedings of the 2001 ACM/IEEE conference on Supercomputing

Page 7

https://doi.org/10.1145/582034.582041

Published: 10 November 2001 Publication History

Abstract

System interconnect is a key determiner of the cost, performance, and reliability of large cache-coherent, shared-memory multiprocessors. Interconnect implementations have to accommodate ever greater numbers of ever faster processors. This paper describes the Sun™ Fireplane two-level cache-coherency protocol, and its use in the medium and large-sized UltraSPARC-III-based Sun Fire™ servers.

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Cited By

Sorin DHill MWood DSorin DHill MWood D(2022)Coherence ProtocolsA Primer on Memory Consistency and Cache Coherence10.1007/978-3-031-01733-9_6(83-97)Online publication date: 18-Oct-2022
https://doi.org/10.1007/978-3-031-01733-9_6
Matthews OSorin DHunter HMoreno JEmer JSanchez D(2017)Architecting hierarchical coherence protocols for push-button parametric verificationProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123971(477-489)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123971
Li ZMohamed MChen XZhou HMickelson AShang LVachharajani M(2011)IrisACM Journal on Emerging Technologies in Computing Systems10.1145/1970406.19704107:2(1-22)Online publication date: 1-Jul-2011
https://dl.acm.org/doi/10.1145/1970406.1970410
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Index Terms

The sun fireplane system interconnect
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
2. Hardware
  1. Integrated circuits
    1. Interconnect
    2. Semiconductor memory
      1. Dynamic memory

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Published In

cover image ACM Conferences

SC '01: Proceedings of the 2001 ACM/IEEE conference on Supercomputing

November 2001

756 pages

ISBN:158113293X

DOI:10.1145/582034

Conference Chair:
Charles Slocomb
Los Alamos National Laboratory

Copyright © 2001 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 November 2001

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SC '01: International Conference for High Performance Computing, Networking, Storage and Analysis

November 10 - 16, 2001

Colorado, Denver

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SC '01 Paper Acceptance Rate 60 of 240 submissions, 25%;

Overall Acceptance Rate 1,516 of 6,373 submissions, 24%

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Citations

Cited By

Sorin DHill MWood DSorin DHill MWood D(2022)Coherence ProtocolsA Primer on Memory Consistency and Cache Coherence10.1007/978-3-031-01733-9_6(83-97)Online publication date: 18-Oct-2022
https://doi.org/10.1007/978-3-031-01733-9_6
Matthews OSorin DHunter HMoreno JEmer JSanchez D(2017)Architecting hierarchical coherence protocols for push-button parametric verificationProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123971(477-489)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123971
Li ZMohamed MChen XZhou HMickelson AShang LVachharajani M(2011)IrisACM Journal on Emerging Technologies in Computing Systems10.1145/1970406.19704107:2(1-22)Online publication date: 1-Jul-2011
https://dl.acm.org/doi/10.1145/1970406.1970410
Kim DAhn JKim JHuh JSalapura VGschwind MKnoop J(2010)Subspace snoopingProceedings of the 19th international conference on Parallel architectures and compilation techniques10.1145/1854273.1854292(111-122)Online publication date: 11-Sep-2010
https://dl.acm.org/doi/10.1145/1854273.1854292
Atoofian EBaniasadi A(2008)Using supplier locality in power-aware interconnects and caches in chip multiprocessorsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2007.09.00554:5(507-518)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1016/j.sysarc.2007.09.005
Tikir MHollingsworth J(2008)Hardware monitors for dynamic page migrationJournal of Parallel and Distributed Computing10.1016/j.jpdc.2008.05.00668:9(1186-1200)Online publication date: 1-Sep-2008
https://dl.acm.org/doi/10.1016/j.jpdc.2008.05.006
Gerritsen MLöf HThiele M(2008)Parallel implementations of streamline simulatorsComputational Geosciences10.1007/s10596-008-9113-y13:1(135-149)Online publication date: 25-Oct-2008
https://doi.org/10.1007/s10596-008-9113-y
Atoofian EBaniasadi AAasaraai KBanerjee UMoreira JDubois MStenström P(2007)Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocolsProceedings of the 4th international conference on Computing frontiers10.1145/1242531.1242568(259-266)Online publication date: 7-May-2007
https://dl.acm.org/doi/10.1145/1242531.1242568
Kırman NKırman MDokania RMartinez JApsel AWatkins MAlbonesi D(2007)On-Chip Optical Technology in Future Bus-Based Multicore DesignsIEEE Micro10.1109/MM.2007.1827:1(56-66)Online publication date: 1-Jan-2007
https://dl.acm.org/doi/10.1109/MM.2007.18
Cantin JSmith JLipasti MMoshovos AFalsafi B(2006)Coarse-Grain Coherence TrackingIEEE Micro10.5555/1116644.111667126:1(70-79)Online publication date: 1-Jan-2006
https://dl.acm.org/doi/10.5555/1116644.1116671
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