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Overlapped loop support in the Cydra 5

Published: 01 April 1989 Publication History
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  • Abstract

    The CydraTM 5 architecture adds unique support for overlapping successive iterations of a loop to a very long instruction word (VLIW) base. This architecture allows highly parallel loop execution for a much larger class of loops than can be vectorized, without requiring the unrolling of loops usually used by compilers for VLIW machines. This paper discusses the Cydra 5 loop scheduling model, the special architectural features which support it, and the loop compilation techniques used to take full advantage of the architecture.

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    • (2000)Selective guarded execution using profiling on a dynamically scheduled processorInnovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650)10.1109/IWIA.1999.898839(15-22)Online publication date: 2000
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    Published In

    cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 17, Issue 2
    Special issue: Proceedings of ASPLOS-III: the third international conference on architecture support for programming languages and operating systems
    April 1989
    291 pages
    ISSN:0163-5964
    DOI:10.1145/68182
    Issue’s Table of Contents
    • cover image ACM Conferences
      ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systems
      April 1989
      303 pages
      ISBN:0897913000
      DOI:10.1145/70082
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 01 April 1989
    Published in SIGARCH Volume 17, Issue 2

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    • (2017)Combining loop unrolling strategies and code predication to reduce the worst-case execution time of real-time softwareApplied Computing and Informatics10.1016/j.aci.2017.03.00213:2(184-193)Online publication date: Jul-2017
    • (2005)Integer loop code generation for VLIWLanguages and Compilers for Parallel Computing10.1007/BFb0014208(318-330)Online publication date: 9-Jun-2005
    • (2000)Selective guarded execution using profiling on a dynamically scheduled processorInnovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650)10.1109/IWIA.1999.898839(15-22)Online publication date: 2000
    • (1999)The effects of predicated execution on architectures supporting dynamic speculationInnovative Architecture for Future Generation High-Performance Processors and Systems10.1109/IWIA.1998.779071(37-45)Online publication date: 1999
    • (1998)Analyzing the individual/combined effects of speculative and guarded execution on a superscalar architectureProceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing10.1109/IPPS.1998.669911(199-208)Online publication date: 1998
    • (1997)Techniques for critical path reduction of scalar programsInternational Journal of Parallel Programming10.1007/BF0270003425:3(147-181)Online publication date: 1-Jun-1997
    • (1994)Profile-assisted instruction schedulingInternational Journal of Parallel Programming10.1007/BF0257787322:2(151-181)Online publication date: 1-Apr-1994
    • (1992)Data flow and dependence analysis for instruction level parallelismLanguages and Compilers for Parallel Computing10.1007/BFb0038668(236-250)Online publication date: 1992
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