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Evaluating the performance of software cache coherence

Authors:

A. AgarwalAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 17, Issue 2

Pages 230 - 242

https://doi.org/10.1145/68182.68204

Published: 01 April 1989 Publication History

Abstract

In a shared-memory multiprocessor with private caches, cached copies of a data item must be kept consistent. This is called cache coherence. Both hardware and software coherence schemes have been proposed. Software techniques are attractive because they avoid hardware complexity and can be used with any processor-memory interconnection. This paper presents an analytical model of the performance of two software coherence schemes and, for comparison, snoopy-cache hardware. The model is validated against address traces from a bus-based multiprocessor. The behavior of the coherence schemes under various workloads is compared, and their sensitivity to variations in workload parameters is assessed. The analysis shows that the performance of software schemes is critically determined by certain parameters of the workload: the proportion of data accesses, the fraction of shared references, and the number of times a shared block is accessed before it is purged from the cache. Snoopy caches are more resilient to variations in these parameters. Thus when evaluating a software scheme as a design alternative, it is essential to consider the characteristics of the expected workload. The performance of the two software schemes with a multistage interconnection network is also evaluated, and it is determined that both scale well.

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Cited By

Wilkins MWestrick SKandiah VBernat ASuchy BDeiana ECampanoni SAcar UDinda PHardavellas NDubach CBruening DHardekopf B(2023)WARDen: Specializing Cache Coherence for High-Level Parallel LanguagesProceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization10.1145/3579990.3580013(122-135)Online publication date: 17-Feb-2023
https://dl.acm.org/doi/10.1145/3579990.3580013
Lopriore L(1989)Software-controlled cache coherence protocol for multicache systemsInformation Processing Letters10.1016/0020-0190(89)90190-733:3(125-130)Online publication date: Nov-1989
https://doi.org/10.1016/0020-0190(89)90190-7
Cunha MMatoussi OPétrot F(2017)Detecting Software Cache Coherence Violations in MPSoC Using Traces Captured on Virtual PlatformsACM Transactions on Embedded Computing Systems10.1145/299019316:2(1-21)Online publication date: 2-Jan-2017
https://dl.acm.org/doi/10.1145/2990193
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Evaluating the performance of software cache coherence

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 17, Issue 2

Special issue: Proceedings of ASPLOS-III: the third international conference on architecture support for programming languages and operating systems

April 1989

291 pages

ISSN:0163-5964

DOI:10.1145/68182

Editor:
Joel Emer

Issue’s Table of Contents

ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systems
April 1989
303 pages
ISBN:0897913000
DOI:10.1145/70082
Chairman:
Joel Emer,
General Chair:
John Hennessy
Stanford University

Copyright © 1989 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1989

Published in SIGARCH Volume 17, Issue 2

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Cited By

Wilkins MWestrick SKandiah VBernat ASuchy BDeiana ECampanoni SAcar UDinda PHardavellas NDubach CBruening DHardekopf B(2023)WARDen: Specializing Cache Coherence for High-Level Parallel LanguagesProceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization10.1145/3579990.3580013(122-135)Online publication date: 17-Feb-2023
https://dl.acm.org/doi/10.1145/3579990.3580013
Lopriore L(1989)Software-controlled cache coherence protocol for multicache systemsInformation Processing Letters10.1016/0020-0190(89)90190-733:3(125-130)Online publication date: Nov-1989
https://doi.org/10.1016/0020-0190(89)90190-7
Cunha MMatoussi OPétrot F(2017)Detecting Software Cache Coherence Violations in MPSoC Using Traces Captured on Virtual PlatformsACM Transactions on Embedded Computing Systems10.1145/299019316:2(1-21)Online publication date: 2-Jan-2017
https://dl.acm.org/doi/10.1145/2990193
Agrawal VDabral APalit TShen YFerdman M(2015)Architectural Support for Dynamic LinkingACM SIGARCH Computer Architecture News10.1145/2786763.269439243:1(691-702)Online publication date: 14-Mar-2015
https://dl.acm.org/doi/10.1145/2786763.2694392
Agrawal VDabral APalit TShen YFerdman M(2015)Architectural Support for Dynamic LinkingACM SIGPLAN Notices10.1145/2775054.269439250:4(691-702)Online publication date: 14-Mar-2015
https://dl.acm.org/doi/10.1145/2775054.2694392
Agrawal VDabral APalit TShen YFerdman MOzturk OEbcioglu KDwarkadas S(2015)Architectural Support for Dynamic LinkingProceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/2694344.2694392(691-702)Online publication date: 14-Mar-2015
https://dl.acm.org/doi/10.1145/2694344.2694392
Ashby TDiaz PCintra M(2011)Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom FiltersIEEE Transactions on Computers10.1109/TC.2010.15560:4(472-483)Online publication date: 1-Apr-2011
https://dl.acm.org/doi/10.1109/TC.2010.155
Rauchwerger LAmato NTorrellas J(2001)SmartApps: An Application Centric Approach to High Performance ComputingLanguages and Compilers for Parallel Computing10.1007/3-540-45574-4_6(82-96)Online publication date: 4-Dec-2001
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Eager DSorin DVernon M(2000)AMVA techniques for high service time variabilityACM SIGMETRICS Performance Evaluation Review10.1145/345063.33941828:1(217-228)Online publication date: 1-Jun-2000
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