Article

Fast processor core selection for WLAN modem using mappability estimation

Authors:

Juha-Pekka Soininen,

Martti ForsellAuthors Info & Claims

CODES '02: Proceedings of the tenth international symposium on Hardware/software codesign

Pages 61 - 66

https://doi.org/10.1145/774789.774803

Published: 06 May 2002 Publication History

Abstract

Mappability metric and a novel method for evaluating the goodness of processor core and algorithm combinations are introduced. The new mappability concept is an addition to performance and cost metrics used in existing codesign and system synthesis approaches. The mappability estimation is based on the analysis of the correlation or similarity of algorithm and core architecture characteristics. It allows fast design space exploration of core architectures and mappings with little modeling effort. The method is demonstrated by analyzing suitable processor core architectures for baseband algorithms of the WLAN modem. 140400 architecture-algorithm pairs were analyzed in total and the estimated results were similar to the results of more detailed evaluations. The method is not, however, limited to the WLAN modem, but is applicable for digital signal processing in general.

References

[1]

Allan, A., et al, "2001 Technology Roadmap for Semiconductors", Computer, Vol. 35., No. I, 2002, pp. 42--53

Digital Library

[2]

Chang, H. et al., Surviving the SOC Revolution - A Guide to Platform-Based Design, Kluwer Academic Publishers, 1999, 235 pp.

Digital Library

[3]

Kreutzer, K. et al., "System Level Design: Orthogonalization of Concerns and Platform Based Design", IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 19, No. 12, December 2000, pp. 1523--1543.

Digital Library

[4]

Hennessy, J.L. & Patterson, D. A., Computer Architecture - A Quantitative Approach, 2nd ed. Morgan Kauffman Publishers Inc, 1996, 760 pp.

Digital Library

[5]

Ernst, R., "'Codesign of Embedded Systems: Status and Trends". IEEE Design and Test of Computers, Vol. 15 No. 2, 1998 pp. 45--53.

Digital Library

[6]

Soininen, J.-P. et al., "Mappability Estimation of Architecture and Algorithm", Proceedings of Design Automation & Test in Europe 2002 Conference, 2002, p. 1132.

Digital Library

[7]

Krishna, C. (ed.), "Performance Modeling for Computer Architects", IEEE CS Press, Los Alamitos, CA, 1996, 391 pp.

Digital Library

[8]

Flynn, M. et al., "Deep-Submicron Microprocessor Design Issues", IEEE Micro, Vol. 19, No. 4, July-August 1999, pp. 11--22.

Digital Library

[9]

Heidelberger, P. & Lavenberg, S., Computer Performance Evaluation Methodology, IEEE Transaction on Computers, Vol. C-33, No. 12, 1984, pp. 1195--1220.

[10]

Gong, J. et al., "Performance evaluation for application- specific architectures", IEEE Transactions on VLSI, Vol. 3, No. 4, December 1995, pp 483--490.

Digital Library

[11]

Suzuki, K. & Sangiovanni-Vincentelli, A., "Efficient Software Performance Estimation Methods for Hardware/Software Codesign", Proceedings of 33rd Design Automation Conference, 1996 pp. 605--610.

Digital Library

[12]

Lazarescu, M. et al., "Compilation-based Software Performance Estimation for System Level Design", Proceedings of High Level Design Validation and Test Workshop, 2000, pp. 167--172.

Digital Library

[13]

Ghazal, N. et al., "Retargetable Estimation Scheme for DSP Architectures", Proceedings of the Asia and South Pacific Design Automation Conference, 2000, pp. 485--489.

Digital Library

[14]

Carro, L. et al., "System Synthesis for Multiprocessor Embedded Applications", Proceedings of Design Automation and Test in Europe, 2000, pp. 697--702.

Digital Library

[15]

Grass, E. et al., "On the Single-Chip Implementation of a Hiperlan/2 and IEEE 802.11a Capable Modem ", IEEE Personal Communications, December 2001, pp. 48--57.

Cited By

Kreku JTiensyrjä KWieferink AVanthournout B(2011)ASIP Exploration and DesignScalable Multi-core Architectures10.1007/978-1-4419-6778-7_4(81-103)Online publication date: 13-Sep-2011
https://doi.org/10.1007/978-1-4419-6778-7_4
Soininen JJantsch AForsell MPelkonen AKreku JKumar S(2003)Extending Platform-Based Design to Network on Chip SystemsProceedings of the 16th International Conference on VLSI Design10.5555/832285.835539Online publication date: 4-Jan-2003
https://dl.acm.org/doi/10.5555/832285.835539
Kreku JSoininen J(2003)Mappability estimate: a measure of the goodness of a processor-algorithm pairProceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)10.1109/ISSOC.2003.1267731(119-122)Online publication date: 2003
https://doi.org/10.1109/ISSOC.2003.1267731
Show More Cited By

Index Terms

Fast processor core selection for WLAN modem using mappability estimation

Recommendations

Selection of instruction set extensions for an FPGA embedded processor core
IPDPS'06: Proceedings of the 20th international conference on Parallel and distributed processing

A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The instruction set of the PowerPC 405 is extended by selecting additional ...
Intel nehalem processor core made FPGA synthesizable
FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-...
Evaluation of Interoperability Criteria and Mechanisms for Seamless Inter-Working Between UMTS-HSDPA and WLAN Networks Enhanced with MIMO Techniques

This article proposes criteria and mechanisms that achieve seamless inter-working between the multi-radio access technologies that will compose the fourth-generation (4G) wireless mobile environment. We address the problem of incorporating system ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

CODES '02: Proceedings of the tenth international symposium on Hardware/software codesign

May 2002

232 pages

ISBN:1581135424

DOI:10.1145/774789

General Chairs:
Joerg Henkel
C & C Research Labs, NEC
,
Xiaobo Sharon Hu
University of Notre Dame
,
Program Chairs:
Rajesh Gupta
University of California, Irvine
,
Sri Parameswaran
University of New South Wales, Australia

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

IFIP WG 10.5: IFIP WG 10.5
IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
SIGSOFT: ACM Special Interest Group on Software Engineering
IEEE-CS\DATC: IEEE Computer Society

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 May 2002

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

CODES02

Sponsor:

IFIP WG 10.5
SIGDA
SIGSOFT
IEEE-CS\DATC

CODES02: 10th International Symposium on Hardware/Software Codesign

May 6 - 8, 2002

Colorado, Estes Park

Acceptance Rates

Overall Acceptance Rate 280 of 864 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
267
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 17 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Kreku JTiensyrjä KWieferink AVanthournout B(2011)ASIP Exploration and DesignScalable Multi-core Architectures10.1007/978-1-4419-6778-7_4(81-103)Online publication date: 13-Sep-2011
https://doi.org/10.1007/978-1-4419-6778-7_4
Soininen JJantsch AForsell MPelkonen AKreku JKumar S(2003)Extending Platform-Based Design to Network on Chip SystemsProceedings of the 16th International Conference on VLSI Design10.5555/832285.835539Online publication date: 4-Jan-2003
https://dl.acm.org/doi/10.5555/832285.835539
Kreku JSoininen J(2003)Mappability estimate: a measure of the goodness of a processor-algorithm pairProceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)10.1109/ISSOC.2003.1267731(119-122)Online publication date: 2003
https://doi.org/10.1109/ISSOC.2003.1267731
Soininen JJantsch AForsell MPelkonen AKreku JKumar S(2003)Extending platform-based design to network on chip systems16th International Conference on VLSI Design, 2003. Proceedings.10.1109/ICVD.2003.1183169(401-408)Online publication date: 2003
https://doi.org/10.1109/ICVD.2003.1183169

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents