Article

Behavioral consistency of C and verilog programs using bounded model checking

Authors:

Edmund Clarke,

Daniel Kroening,

Karen YoravAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 368 - 371

https://doi.org/10.1145/775832.775928

Published: 02 June 2003 Publication History

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E. Clarke, D. Kroening, and K. Yorav. Behavioral consistency of C and Verilog programs using Bounded Model Checking. Technical Report CMU-CS-03-126, Carnegie Mellon University, School of Computer Science, 2003.]]

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Orvalho PJanota MManquinho V(2024)cfaults: Model-Based Diagnosis for Fault Localization in C with Multiple Test CasesFormal Methods10.1007/978-3-031-71162-6_24(463-481)Online publication date: 9-Sep-2024
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Reinhard TFasse JJacobs BFerrara PHadarean L(2023)Completeness Thresholds for Memory Safety of Array Traversing ProgramsProceedings of the 12th ACM SIGPLAN International Workshop on the State Of the Art in Program Analysis10.1145/3589250.3596143(47-54)Online publication date: 6-Jun-2023
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Brauckmann APolgreen EGrosser TO'Boyle M(2023)mlirSynth: Automatic, Retargetable Program Raising in Multi-Level IR Using Program Synthesis2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00012(39-50)Online publication date: 21-Oct-2023
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Index Terms

Behavioral consistency of C and verilog programs using bounded model checking
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
2. Theory of computation
  1. Logic
  2. Semantics and reasoning
    1. Program reasoning

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Published In

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 02 June 2003

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DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Orvalho PJanota MManquinho V(2024)cfaults: Model-Based Diagnosis for Fault Localization in C with Multiple Test CasesFormal Methods10.1007/978-3-031-71162-6_24(463-481)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1007/978-3-031-71162-6_24
Reinhard TFasse JJacobs BFerrara PHadarean L(2023)Completeness Thresholds for Memory Safety of Array Traversing ProgramsProceedings of the 12th ACM SIGPLAN International Workshop on the State Of the Art in Program Analysis10.1145/3589250.3596143(47-54)Online publication date: 6-Jun-2023
https://dl.acm.org/doi/10.1145/3589250.3596143
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Equivalence checking between function block diagrams and C programs using HW-CBMC

HW/SW co-verification of embedded systems using bounded model checking

Word level predicate abstraction and refinement for verifying RTL verilog

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Equivalence checking between function block diagrams and C programs using HW-CBMC

HW/SW co-verification of embedded systems using bounded model checking

Word level predicate abstraction and refinement for verifying RTL verilog

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