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Flexible architectures for engineering successful SOCs

Published: 07 June 2004 Publication History

Abstract

This paper focuses on a particular SOC design technology and methodology, here called the advanced or processor-centric SOC design method, which reduces the risk of SOC design and increases ROI by using configurable processors to implement on-chip functions while increasing the SOC's flexibility through software programmability. The essential enabler for this design methodology is automatic processor generation-the rapid and easy creation of new microprocessor architectures, complete with efficient hardware designs and comprehensive software tools. The high speed of the generation process and the great flexibility of the generated architectures underpin a fundamental shift of the role of processors in system architecture.

Cited By

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  • (2013)SWSLProceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems10.5555/2537857.2537890(191-202)Online publication date: 21-Oct-2013
  • (2013)SWSL: SoftWare Synthesis for network LookupArchitectures for Networking and Communications Systems10.1109/ANCS.2013.6665201(191-201)Online publication date: Oct-2013
  • (2012)Methodology for Analyzing and Mapping Complex Algorithms for Small SatellitesAIAA Infotech@Aerospace Conference10.2514/6.2009-1845Online publication date: 14-Jun-2012
  • Show More Cited By

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  1. Flexible architectures for engineering successful SOCs

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    Published In

    cover image ACM Conferences
    DAC '04: Proceedings of the 41st annual Design Automation Conference
    June 2004
    1002 pages
    ISBN:1581138288
    DOI:10.1145/996566
    • General Chair:
    • Sharad Malik,
    • Program Chairs:
    • Limor Fix,
    • Andrew B. Kahng
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 07 June 2004

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    Author Tags

    1. MPSOC
    2. RISC
    3. RTL
    4. SOC
    5. processor cores

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    DAC04
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    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    Cited By

    View all
    • (2013)SWSLProceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems10.5555/2537857.2537890(191-202)Online publication date: 21-Oct-2013
    • (2013)SWSL: SoftWare Synthesis for network LookupArchitectures for Networking and Communications Systems10.1109/ANCS.2013.6665201(191-201)Online publication date: Oct-2013
    • (2012)Methodology for Analyzing and Mapping Complex Algorithms for Small SatellitesAIAA Infotech@Aerospace Conference10.2514/6.2009-1845Online publication date: 14-Jun-2012
    • (2011)Understanding sources of ineffciency in general-purpose chipsCommunications of the ACM10.1145/2001269.200129154:10(85-93)Online publication date: 1-Oct-2011
    • (2011)How sensitive is processor customization to the workload's input datasets?Proceedings of the 2011 IEEE 9th Symposium on Application Specific Processors10.1109/SASP.2011.5941070(1-7)Online publication date: 5-Jun-2011
    • (2010)Understanding sources of inefficiency in general-purpose chipsACM SIGARCH Computer Architecture News10.1145/1816038.181596838:3(37-47)Online publication date: 19-Jun-2010
    • (2010)Understanding sources of inefficiency in general-purpose chipsProceedings of the 37th annual international symposium on Computer architecture10.1145/1815961.1815968(37-47)Online publication date: 19-Jun-2010
    • (2008)An Automated Design Flow for NoC-based MPSoCs on FPGAProceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping10.1109/RSP.2008.31(58-64)Online publication date: 2-Jun-2008
    • (2007)Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chipProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266393(117-122)Online publication date: 16-Apr-2007
    • (2007)An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip2007 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2007.364577(1-6)Online publication date: Apr-2007
    • Show More Cited By

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