Article

Heterogeneous MP-SoC: the solution to energy-efficient signal processing

Authors:

Heinrich MeyrAuthors Info & Claims

DAC '04: Proceedings of the 41st annual Design Automation Conference

Pages 686 - 691

https://doi.org/10.1145/996566.996754

Published: 07 June 2004 Publication History

Abstract

To meet conflicting flexibility, performance and cost constraints of demanding signal processing applications, future designs in this domain will contain an increasing number of application specific programmable units combined with complex communication and memory infrastructures. Novel architecture trends like Application Specific Instruction-set Processors (ASIPs) as well as customized buses and Network-on-Chip based communication promise enormous potential for optimization. However, state-of-the-art tooling and design practice is not in a shape to take advantage of this advances in computer architecture and silicon technology. Currently, EDA industry develops two diverging strategies to cope with the design complexity of such application specific, heterogeneous MP-SoC platforms. First, the IP-driven approach emphasizes the composition of MP-SoC platforms from configurable off-the-shelf Intellectual Property blocks. On the other hand, the design-driven approach strives to take design efficiency to the required level by use of system level design methodologies and IP generation tools. In this paper, we discuss technical and economical aspects of both strategies. Based on the analysis of recent trends in computer architecture and system level design, we envision a hand-in-hand approach of signal processing platform architectures and design metholodgy to conquer the complexity crisis in emerging MP-SoC developments.

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Cited By

Kempf TAscheid GLeupers RKempf TAscheid GLeupers R(2011)Systems for Wireless CommunicationMultiprocessor Systems on Chip10.1007/978-1-4419-8153-0_2(7-22)Online publication date: 10-Jan-2011
https://doi.org/10.1007/978-1-4419-8153-0_2
Nácul ARegazzoni FLajolo MLauwereins RMadsen J(2007)Hardware scheduling support in SMP architecturesProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266502(642-647)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266502

Index Terms

Heterogeneous MP-SoC: the solution to energy-efficient signal processing
1. Computer systems organization
2. Computing methodologies
  1. Modeling and simulation

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Information

Published In

cover image ACM Conferences

DAC '04: Proceedings of the 41st annual Design Automation Conference

June 2004

1002 pages

ISBN:1581138288

DOI:10.1145/996566

General Chair:
Sharad Malik
Princeton University, Princeton, NJ
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Andrew B. Kahng
University of California at San Diego, La Jolla, CA

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 June 2004

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Cited By

Kempf TAscheid GLeupers RKempf TAscheid GLeupers R(2011)Systems for Wireless CommunicationMultiprocessor Systems on Chip10.1007/978-1-4419-8153-0_2(7-22)Online publication date: 10-Jan-2011
https://doi.org/10.1007/978-1-4419-8153-0_2
Nácul ARegazzoni FLajolo MLauwereins RMadsen J(2007)Hardware scheduling support in SMP architecturesProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266502(642-647)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266502

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