Article

A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms

Authors:

Andreas Wieferink,

Rainer Leupers,

Achim NohlAuthors Info & Claims

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 2

Page 21256

Published: 16 February 2004 Publication History

Abstract

Current and future SoC designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility,performance and cost constraints. Designing such a heterogenous MP-SoC architecture bears enormous potential for optimization, but requires a system-level design environment andmethodology to evaluate architectural alternatives. This paper proposes a methodology to jointly design and optimize the processor architecture together with the on-chip communicationbased on the LISA Processor Design Platform in combination with SystemC Transaction Level Models. The proposed methodology advocates a successive refinement flow of the system-level models of both the processor cores and the communication architecture. This allows design decisions based on the best modeling ef.ciency, accuracy and simulation performance possible on the respective abstraction level. The effectiveness of our approach is demonstrated by the exemplary design of a dual-processor JPEG decoding system.

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Cited By

Holt JDastidar JLindberg DPape JYang P(2012)A full lifecycle performance verification methodology for multicore systems-on-chipACM Transactions on Design Automation of Electronic Systems10.1145/2209291.220929417:3(1-18)Online publication date: 5-Jul-2012
https://dl.acm.org/doi/10.1145/2209291.2209294
Ventroux NSassolas TGuerre ACreusillet BKeryell RPérez DNiar SSilvano CAbhari M(2012)SESAM/Par4AllProceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2162131.2162133(9-16)Online publication date: 23-Jan-2012
https://dl.acm.org/doi/10.1145/2162131.2162133
Gerstlauer ASchirner GLin Y(2010)Platform modeling for exploration and synthesisProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899889(725-731)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899889
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Index Terms

A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms

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Published In

cover image ACM Conferences

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 2

February 2004

606 pages

ISBN:0769520855

Copyright © Copyright (c) 2004 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

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Published: 16 February 2004

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DATE04: Design, Automation and Test in Europe 2004

February 16 - 20, 2004

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Holt JDastidar JLindberg DPape JYang P(2012)A full lifecycle performance verification methodology for multicore systems-on-chipACM Transactions on Design Automation of Electronic Systems10.1145/2209291.220929417:3(1-18)Online publication date: 5-Jul-2012
https://dl.acm.org/doi/10.1145/2209291.2209294
Ventroux NSassolas TGuerre ACreusillet BKeryell RPérez DNiar SSilvano CAbhari M(2012)SESAM/Par4AllProceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2162131.2162133(9-16)Online publication date: 23-Jan-2012
https://dl.acm.org/doi/10.1145/2162131.2162133
Gerstlauer ASchirner GLin Y(2010)Platform modeling for exploration and synthesisProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899889(725-731)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899889
Sauer CGries MLöb HFix L(2008)SystemClickProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391593(480-485)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391593
Scharwaechter HKammler DWieferink AHohenauer MKaruri KCeng JLeupers RAscheid GMeyr H(2007)ASIP architecture exploration for efficient IPSec encryptionACM Transactions on Embedded Computing Systems10.1145/1234675.12346796:2(12-es)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1145/1234675.1234679
Angiolini FCeng JLeupers RFerrari FFerri CBenini LGielen G(2006)An integrated open framework for heterogeneous MPSoC design space explorationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131797(1145-1150)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131797
Bjerregaard TMahadevan S(2006)A survey of research and practices of Network-on-chipACM Computing Surveys10.1145/1132952.113295338:1(1-es)Online publication date: 29-Jun-2006
https://dl.acm.org/doi/10.1145/1132952.1132953
Sonntag SGries MSauer C(2006)Performance Evaluation of Packet Processing Architectures Using Multiclass Queuing NetworksProceedings of the 39th annual Symposium on Simulation10.1109/ANSS.2006.35(80-89)Online publication date: 2-Apr-2006
https://dl.acm.org/doi/10.1109/ANSS.2006.35
Wieferink ALeupers RAscheid GMeyr HMichiels TNohl AKogel TEles PJantsch ABergamaschi R(2005)Retargetable generation of TLM bus interfaces for MP-SoC platformsProceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1084834.1084898(249-254)Online publication date: 19-Sep-2005
https://dl.acm.org/doi/10.1145/1084834.1084898
Rissa TDonlin ALuk W(2005)Evaluation of SystemC Modelling of Reconfigurable Embedded SystemsProceedings of the conference on Design, Automation and Test in Europe - Volume 310.1109/DATE.2005.143(253-258)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.143
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