Article

Retargetable generation of TLM bus interfaces for MP-SoC platforms

Authors:

Andreas Wieferink,

Rainer Leupers,

Tim KogelAuthors Info & Claims

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 249 - 254

https://doi.org/10.1145/1084834.1084898

Published: 19 September 2005 Publication History

Abstract

In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cores combined with a complex communication architecture. Optimal platforms are obtained by customizing both computation and communication modules to the application's needs. In our design flow both kinds of SoC modules are automatically derived from abstract specifications. This work focuses on generating the communication adaptors, which are tailored to the processor as well as to the bus side. For early system simulation, the adaptors are capable of bridging an abstraction gap by implementing a bus interface state machine. The generated processor cores, adaptors and bus nodes are applied in the exemplary design of a JPEG decoding platform.

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Cited By

Zimmermann JBringmann OBraun ARosenstiel W(2009)Integration of high-level synthesis in ESL platform modeling by automated generation of protocol adapters2009 International Conference on Communications, Circuits and Systems10.1109/ICCCAS.2009.5250310(1149-1154)Online publication date: Jul-2009
https://doi.org/10.1109/ICCCAS.2009.5250310
Posadas HVillar E(2009)Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulationAnalysis, Architectures and Modelling of Embedded Systems10.1007/978-3-642-04284-3_2(12-23)Online publication date: 2009
https://doi.org/10.1007/978-3-642-04284-3_2
Pasricha SDutt N(2008)On-Chip Communication Architecture Refinement and Interface SynthesisOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00009-8(341-366)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00009-8

Index Terms

Retargetable generation of TLM bus interfaces for MP-SoC platforms

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cover image ACM Conferences

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

September 2005

356 pages

ISBN:1595931619

DOI:10.1145/1084834

General Chairs:
Petru Eles
Linköping University, Sweden
,
Axel Jantsch
Royal Institute of Technology, Sweden
,
Program Chair:
Reinaldo Bergamaschi
IBM T. J. Watson Research Center

Copyright © 2005 ACM.

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Published: 19 September 2005

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CODES/ISSS05: Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

September 19 - 21, 2005

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Zimmermann JBringmann OBraun ARosenstiel W(2009)Integration of high-level synthesis in ESL platform modeling by automated generation of protocol adapters2009 International Conference on Communications, Circuits and Systems10.1109/ICCCAS.2009.5250310(1149-1154)Online publication date: Jul-2009
https://doi.org/10.1109/ICCCAS.2009.5250310
Posadas HVillar E(2009)Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulationAnalysis, Architectures and Modelling of Embedded Systems10.1007/978-3-642-04284-3_2(12-23)Online publication date: 2009
https://doi.org/10.1007/978-3-642-04284-3_2
Pasricha SDutt N(2008)On-Chip Communication Architecture Refinement and Interface SynthesisOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00009-8(341-366)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00009-8

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