research-article

SESAM/Par4All: a tool for joint exploration of MPSoC architectures and dynamic dataflow code generation

Authors:

R. KeryellAuthors Info & Claims

RAPIDO '12: Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

Pages 9 - 16

https://doi.org/10.1145/2162131.2162133

Published: 23 January 2012 Publication History

Abstract

Due to the increasing complexity of new multiprocessor systems on chip, flexible and accurate simulators become a necessity for exploring the vast design space solution. In a streaming execution model, only a well-balanced pipeline can lead to an efficient implementation. However with dynamic applications, each stage is prone to execution time variations. Only a joint exploration of the application space of parallelization possibilities, together with the possible MPSoC architectural choices, can lead to an efficient embedded system. In this paper, we associate a semi-automatic parallelization workflow based on the Par4All retargetable compiler, to the SESAM environment. This new framework can ease the application exploration and find the best tradeoffs between complexity and performance for asymmetric homogeneous MPSoCs and dynamic streaming application processing. A use case is performed with a radio sensing application implemented on a complete MPSoC platform.

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SESAM/Par4All: a tool for joint exploration of MPSoC architectures and dynamic dataflow code generation

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cover image ACM Other conferences

RAPIDO '12: Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

January 2012

44 pages

ISBN:9781450311144

DOI:10.1145/2162131

Conference Chairs:
Daniel Gracia Pérez
CEA LIST, France
,
Smail Niar
University of Valenciennes/INRIA, France
,
Cristina Silvano
Politecnico di Milano, Italy
,
Morteza Biglari Abhari
The University of Auckland, New Zealand

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 January 2012

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RAPIDO '12: Methods and Tools

January 23, 2012

Paris, France

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Cited By

Wu SKumano SMarume KEdahiro M(2024)Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based ParallelizationIEEE Access10.1109/ACCESS.2024.337390212(35779-35795)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3373902
Pinto PBispo JCardoso JBarbosa JGadioli DPalermo GMartinovic JGolasowski MSlaninova KCmar RSilvano C(2022)Pegasus: Performance Engineering for Software Applications Targeting HPC SystemsIEEE Transactions on Software Engineering10.1109/TSE.2020.300125748:3(732-754)Online publication date: 1-Mar-2022
https://doi.org/10.1109/TSE.2020.3001257
Usman Ashraf MAlburaei Eassa FJ. Osterweil LAhmad Albeshri AAlgarni AIlyas I(2021)AAP4All: An Adaptive Auto Parallelization of Serial Code for HPC SystemsIntelligent Automation & Soft Computing10.32604/iasc.2021.01904429:3(615-639)Online publication date: 2021
https://doi.org/10.32604/iasc.2021.019044
Huang FYang HTao JWang JTan X(2021)Preliminary study on the automatic parallelism optimization model for image enhancement algorithms based on Intel's® Xeon PhiConcurrency and Computation: Practice and Experience10.1002/cpe.626033:16Online publication date: 6-May-2021
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Harel RMosseri ILevin HAlon LRusanovsky MOren G(2019)Source-to-Source Parallelization Compilers for Scientific Shared-Memory Multi-core and Accelerated Multiprocessing: Analysis, Pitfalls, Enhancement and PotentialInternational Journal of Parallel Programming10.1007/s10766-019-00640-3Online publication date: 8-Aug-2019
https://doi.org/10.1007/s10766-019-00640-3
Prema SNasre RJehadeesan RPanigrahi B(2019)A study on popular auto‐parallelization frameworksConcurrency and Computation: Practice and Experience10.1002/cpe.516831:17Online publication date: 11-Feb-2019
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Arabnejad HBispo JBarbosa JCardoso J(2018)AutoPar-ClavaProceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms10.1145/3183767.3183770(13-19)Online publication date: 23-Jan-2018
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Prema SJehadeesan RPanigrahi B(2017)Identifying pitfalls in automatic parallelization of NAS parallel benchmarks2017 National Conference on Parallel Computing Technologies (PARCOMPTECH)10.1109/PARCOMPTECH.2017.8068329(1-6)Online publication date: Feb-2017
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Alali AAssayad ISadik M(2016)Multilevel MPSoC Performance Evaluation, ISS Model with Timing and Priority ManagementAdvances in Ubiquitous Networking10.1007/978-981-287-990-5_34(425-437)Online publication date: 2-Feb-2016
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Irigoin FJouvelot PTriolet R(2014)Author retrospective for semantical interprocedural parallelizationACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2591645(12-14)Online publication date: 10-Jun-2014
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