research-article

A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels

Authors:

Andy D. Pimentel,

Simon PolstraAuthors Info & Claims

IEEE Transactions on Computers, Volume 55, Issue 2

Pages 99 - 112

https://doi.org/10.1109/TC.2006.16

Published: 01 February 2006 Publication History

Abstract

The sheer complexity of today's embedded systems forces designers to start with modeling and simulating system components and their interactions in the very early design stages. It is therefore imperative to have good tools for exploring a wide range of design choices, especially during the early design stages, where the design space is at its largest. This paper presents an overview of the Sesame framework, which provides high-level modeling and simulation methods and tools for system-level performance evaluation and exploration of heterogeneous embedded systems. More specifically, we describe Sesame's modeling methodology and trajectory. It takes a designer systematically along the path from selecting candidate architectures, using analytical modeling and multiobjective optimization, to simulating these candidate architectures with our system-level simulation environment. This simulation environment subsequently allows for architectural exploration at different levels of abstraction while maintaining high-level and architecture-independent application specifications. We illustrate all these aspects using a case study in which we traverse Sesame's exploration trajectory for a Motion-JPEG encoder application.

References

[1]

F. Vahid and T. Givargis, “Platform Tuning for Embedded Systems Design,” Computer, vol. 34, no. 3, pp. 112-114, Mar. 2001.

Digital Library

[2]

A. Sangiovanni-Vincentelli and G. Martin, “Platform-Based Design and Software Design Methodology for Embedded Systems,” IEEE Design and Test of Computers, vol. 18, no. 6, pp. 23-33, 2001.

Digital Library

[3]

K. Keutzer, S. Malik, A. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli, “System Level Design: Orthogonalization of Concerns and Platform-Based Design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, pp. 1523-1543, Dec. 2000.

Digital Library

[4]

A.D. Pimentel, P. Lieverse, P. van der Wolf, L.O. Hertzberger, and E.F. Deprettere, “Exploring Embedded-Systems Architectures with Artemis,” Computer, vol. 34, no. 11, pp. 57-63, Nov. 2001.

Digital Library

[5]

A.D. Pimentel, “The Artemis Workbench for System-Level Performance Evaluation of Embedded Systems,” Int'l J. Embedded Systems, vol. 1, no. 7, 2005.

[6]

F. Balarin, E. Sentovich, M. Chiodo, P. Giusto, H. Hsieh, B. Tabbara, A. Jurecska, L. Lavagno, C. Passerone, K. Suzuki, and A. Sangiovanni-Vincentelli, Hardware-Software Co-Design of Embedded Systems— The POLIS Approach. Kluwer Academic, 1997.

Digital Library

[7]

F. Balarin, Y. Watanabe, H. Hsieh, L. Lavagno, C. Passerone, and A. Sangiovanni-Vincentelli, “Metropolis: An Integrated Electronic System Design Environment,” Computer, vol. 36, no. 4, pp. 45-52, Apr. 2003.

Digital Library

[8]

A. Mihal, C. Kulkarni, C. Sauer, K. Vissers, M. Moskewicz, M. Tsai, N. Shah, S. Weber, Y. Jin, K. Keutzer, and S. Malik, “Developing Architectural Platforms: A Disciplined Approach,” IEEE Design and Test of Computers, vol. 19, no. 6, pp. 6-16, Nov./Dec. 2002.

Digital Library

[9]

A. Cassidy, J. Paul, and D. Thomas, “Layered, Multi-Threaded, High-Level Performance Design,” Proc. Int'l Conf. Design, Automation and Test in Europe (DATE), Mar. 2003.

Digital Library

[10]

S. Mohanty and V.K. Prasanna, “Rapid System-Level Performance Evaluation and Optimization for Application Mapping onto SoC Architectures,” Proc. IEEE Int'l ASIC/SOC Conf., 2002.

[11]

T. Kogel, A. Wieferink, R. Leupers, G. Ascheid, H. Meyr, D. Bussaglia, and M. Ariyamparambath, “Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs,” Proc. Int'l Workshop Systems, Architectures, Modeling, and Simulation (SAMOS), pp. 138-148, 2003.

[12]

M. Gries, “Methods for Evaluating and Covering the Design Space during Early Design Development,” Integration, the VLSI J., vol. 38, no. 2, pp. 131-183, 2004.

Digital Library

[13]

K. Lahiri, A. Raghunathan, and S. Dey, “System-Level Performance Analysis for Designing On-Chip Communication Architectures,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 6, pp. 768-783, June 2001.

Digital Library

[14]

V. Živković, E.F. Deprettere, P. van der Wolf, and E. de Kock, “Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs,” Proc. Int'l Conf. Design, Automation and Test in Europe (DATE), Mar. 2003.

Digital Library

[15]

P. Lieverse, P. van der Wolf, E.F. Deprettere, and K.A. Vissers, “A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems,” J. VLSI Signal Processing for Signal, Image, and Video Technology, vol. 29, no. 3, pp. 197-207, Nov. 2001.

Digital Library

[16]

J.T. Buck, S. Ha, E.A. Lee, and D.G. Messerschmitt, “Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems,” Int'l J. Computer Simulation, vol. 4, pp. 155-182, Apr. 1994.

[17]

C.A.R. Hoare, “Communicating Sequential Processes,” Comm. ACM, vol. 21, no. 8, Aug. 1978.

Digital Library

[18]

E.A. Lee and T.M. Parks, “Dataflow Process Networks,” Proc. IEEE, vol. 83, no. 5, pp. 773-801, May 1995.

[19]

G. Kahn, “The Semantics of a Simple Language for Parallel Programming,” Proc. IFIP Congress 74, 1974.

[20]

L. Thiele, S. Chakraborty, M. Gries, and S. Künzli, “A Framework for Evaluating Design Tradeoffs in Packet Processing Architectures,” Proc. Design Automation Conf. (DAC), June 2002.

Digital Library

[21]

R.P. Dick and N.K. Jha, “MOGAC: A Multiobjective Genetic Algorithm for Hardware-Software Co-Synthesis of Distributed Embedded Systems,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Oct. 1998.

Digital Library

[22]

T. Blickle, J. Teich, and L. Thiele, “System-Level Synthesis Using Evolutionary Algorithms,” Design Automation for Embedded Systems, vol. 3, no. 1, pp. 23-58, 1998.

Digital Library

[23]

G. Ascia, V. Catania, and M. Palesi, “A GA-Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms,” IEEE Trans. Evolutionary Computation, vol. 8, no. 4, pp. 329-346, 2004.

Digital Library

[24]

T. Givargis and F. Vahid, “Platune: A Tuning Framework for System-on-a-Chip Platforms,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 11, pp. 1317-1327, 2002.

Digital Library

[25]

T. Givargis, F. Vahid, and J. Henkel, “System-Level Exploration for Pareto-Optimal Configurations in Parameterized System-on-a-Chip,” IEEE Trans. Very Large Scale Integration Systems, vol. 10, no. 4, pp. 416-422, 2002.

Digital Library

[26]

J. Peng, S. Abdi, and D. Gajski, “Automatic Model Refinement for Fast Architecture Exploration,” Proc. Int'l Conf. VLSI Design, pp. 332-337, Jan. 2002.

Digital Library

[27]

S. Abdi, D. Shin, and D. Gajski, “Automatic Communication Refinement for System Level Design,” Proc. Design Automation Conf. (DAC), pp. 300-305, June 2003.

Digital Library

[28]

P. Lieverse, P. van der Wolf, and E.F. Deprettere, “A Trace Transformation Technique for Communication Refinement,” Proc. Int'l Symp. Hardware/Software Codesign (CODES), pp. 134-139, Apr. 2001.

Digital Library

[29]

G. Nicolescu, S. Yoo, and A.A. Jerraya, “Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design,” Proc. Int'l Conf. Design, Automation and Test in Europe (DATE), Mar. 2001.

Digital Library

[30]

J.Y. Brunel, E.A. de Kock, W. Kruijtzer, H. Kenter, and W. Smits, “Communication Refinement in Video Systems on Chip,” Proc. Int'l Workshop Hardware/Software Codesign (CODES), pp. 142-146, May 1999.

Digital Library

[31]

J. Rowson and A. Sangiovanni-Vincentelli, “Interface-Based Design,” Proc. Design Automation Conf. (DAC), June 1997.

Digital Library

[32]

B. Kienhuis, E.F. Deprettere, K.A. Vissers, and P. van der Wolf, “An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures,” Proc. Int'l Conf. Application-Specific Systems, Architectures, and Processors (ASAP), July 1997.

Digital Library

[33]

B. Kienhuis, E.F. Deprettere, P. van der Wolf, and K.A. Vissers, “A Methodology to Design Programmable Embedded Systems: The Y-Chart Approach,” Embedded Processor Design Challenges, pp. 18-37, Springer, 2002.

Digital Library

[34]

C. Erbas, S.C. Erbas, and A.D. Pimentel, “A Multiobjective Optimization Model for Exploring Multiprocessor Mappings of Process Networks,” Proc. Int'l Conf. HW/SW Codesign and System Synthesis (CODES-ISSS), pp. 182-187, Oct. 2003.

Digital Library

[35]

E. Zitzler, M. Laumanns, and L. Thiele, “SPEA2: Improving the Strength Pareto Evolutionary Algorithm for Multiobjective Optimization,” Evolutionary Methods for Design, Optimisation, and Control, pp. 95-100, Barcelona: CIMNE, 2002.

[36]

A.D. Pimentel, S. Polstra, F. Terpstra, A.W. van Halderen, J.E. Coffland, and L.O. Hertzberger, “Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems,” Embedded Processor Design Challenges, pp. 57-73, Springer, 2002.

Digital Library

[37]

J.E. Coffland and A.D. Pimentel, “A Software Framework for Efficient System-Level Performance Evaluation of Embedded Systems,” Proc. ACM Symp. Applied Computing (SAC), pp. 666-671, Mar. 2003,

Digital Library

[38]

A. Turjan, B. Kienhuis, and E.F. Deprettere, “Translating Affine Nested Loop Programs to Process Networks,” Proc. Int'l Conf. Compilers, Architectures, and Synthesis for Embedded Systems (CASES), Sept. 2004.

Digital Library

[39]

T. Stefanov and E.F. Deprettere, “Deriving Process Networks from Weakly Dynamic Applications in System-Level Design,” Proc. Int'l Conf. HW/SW Codesign and System Synthesis (CODES-ISSS), Oct. 2003.

Digital Library

[40]

E.A. Lee and S. Neuendorffer, “MoML— a Modeling Markup Language in XML, version 0.4,” Technical Report UCB/ERL M00/8, Electronics Research Lab, Univ. of California, Berkeley, Mar. 2000.

[41]

L. Cai and D. Gajski, “Transaction Level Modeling: An Overview,” Proc. Int'l Conf. HW/SW Codesign and System Synthesis (CODES-ISSS), pp. 19-24, Oct. 2003.

Digital Library

[42]

T. Grötker, S. Liao, G. Martin, and S. Swan, System Design with SystemC. Kluwer Academic, 2002.

Digital Library

[43]

H.L. Muller, “Simulating Computer Architectures,” PhD thesis, Dept. of Computer Science, Univ. of Amsterdam, Feb. 1993.

[44]

M. Thompson and A.D. Pimentel, “A High-Level Programming Paradigm for SystemC,” Proc. Int'l Workshop Systems, Architectures, MOdeling, and Simulation (SAMOS), pp. 530-539, July 2004.

[45]

A.D. Pimentel and C. Erbas, “An IDF-Based Trace Transformation Method for Communication Refinement,” Proc. Design Automation Conf. (DAC), pp. 402-407, June 2003.

Digital Library

[46]

C. Erbas and A.D. Pimentel, “Utilizing Synthesis Methods in Accurate System-Level Exploration of Heterogeneous Embedded Systems,” Proc. IEEE Workshop Signal Processing Systems (SiPS), pp. 310-315, Aug. 2003.

[47]

C. Erbas, S. Polstra, and A.D. Pimentel, “IDF Models for Trace Transformations: A Case Study in Computational Refinement,” Proc. Int'l Workshop Systems, Architectures, MOdeling, and Simulation (SAMOS), pp. 178-187, July 2003.

[48]

E.A. Lee and D.G. Messerschmitt, “Synchronous Data Flow,” Proc. IEEE, vol. 75, no. 9, pp. 1235-1245, Sept. 1987.

[49]

J.T. Buck, “Static Scheduling and Code Generation from Dynamic Dataflow Graphs with Integer Valued Control Streams,” Proc. Asilomar Conf. Signals, Systems, and Computers, Oct. 1994.

[50]

S. Bleuler, M. Laumanns, L. Thiele, and E. Zitzler, “PISA— A Platform and Programming Language Independent Interface for Search Algorithms,” Proc. Evolutionary Multi-Criterion Optimization (EMO 2003), pp. 494-508, 2003.

Digital Library

[51]

A.D. Pimentel, F.P. Terpstra, S. Polstra, and J.E. Coffland, “On the Modeling of Intra-Task Parallelism in Task-Level Parallel Embedded Systems,” Domain-Specific Processors, pp. 85-105, Marcel Dekker, 2003.

Cited By

Menard CLohstroh MBateni SChorlian MDeng ADonovan PFournier CLin SSuchert FTanneberger TKim HCastrillon JLee E(2023)High-performance Deterministic Concurrency Using Lingua FrancaACM Transactions on Architecture and Code Optimization10.1145/361768720:4(1-29)Online publication date: 26-Oct-2023
https://dl.acm.org/doi/10.1145/3617687
Krishnakumar AOgras UMarculescu RKishinevsky MMudge T(2023)Domain-Specific Architectures: Research Problems and Promising ApproachesACM Transactions on Embedded Computing Systems10.1145/356394622:2(1-26)Online publication date: 24-Jan-2023
https://dl.acm.org/doi/10.1145/3563946
Boroujerdian BJing YTripathy DKumar ASubramanian LYen LLee VVenkatesan VJindal AShearer RReddi V(2023)FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip ComplexityACM Transactions on Embedded Computing Systems10.1145/354401622:2(1-35)Online publication date: 24-Jan-2023
https://dl.acm.org/doi/10.1145/3544016
Show More Cited By

Index Terms

A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems
2. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation
  2. Hardware validation

Recommendations

Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations

Simulators have become an integral part of the computer architecture research and design process. Since they have the advantages of cost, time, and flexibility, architects use them to guide design space exploration and to quantify the efficacy of an ...
Accurate Functional-First Multicore Simulators

Fast and accurate simulation of multicore systems requires a parallelized simulator. This paper describes a novel method to build cycle-accurate-capable and parallelizable functional-first simulators of multicore targets.
On the simulation of large-scale architectures using multiple application abstraction levels
Special Issue on High-Performance Embedded Architectures and Compilers

Simulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not suitable for simulating large-...

Comments

Information & Contributors

Information

Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 55, Issue 2

February 2006

143 pages

ISSN:0018-9340

Issue’s Table of Contents

Copyright © 2006.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 February 2006

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

111
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 28 Jul 2024

Other Metrics

View Author Metrics

Citations

Cited By

Menard CLohstroh MBateni SChorlian MDeng ADonovan PFournier CLin SSuchert FTanneberger TKim HCastrillon JLee E(2023)High-performance Deterministic Concurrency Using Lingua FrancaACM Transactions on Architecture and Code Optimization10.1145/361768720:4(1-29)Online publication date: 26-Oct-2023
https://dl.acm.org/doi/10.1145/3617687
Krishnakumar AOgras UMarculescu RKishinevsky MMudge T(2023)Domain-Specific Architectures: Research Problems and Promising ApproachesACM Transactions on Embedded Computing Systems10.1145/356394622:2(1-26)Online publication date: 24-Jan-2023
https://dl.acm.org/doi/10.1145/3563946
Boroujerdian BJing YTripathy DKumar ASubramanian LYen LLee VVenkatesan VJindal AShearer RReddi V(2023)FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip ComplexityACM Transactions on Embedded Computing Systems10.1145/354401622:2(1-35)Online publication date: 24-Jan-2023
https://dl.acm.org/doi/10.1145/3544016
Morais BZhang JSchirner G(2023)TSAR-ILP: Tile-Based, Synchronization-AwaRe ILP Allocating Heterogeneous Platforms for Streaming ApplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.327405042:11(3693-3706)Online publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3274050
Kelefouras VDjemame K(2022)Workflow simulation and multi-threading aware task scheduling for heterogeneous computingJournal of Parallel and Distributed Computing10.1016/j.jpdc.2022.05.011168:C(17-32)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1016/j.jpdc.2022.05.011
Raji MNikseresht M(2022)UMOTS: an uncertainty-aware multi-objective genetic algorithm-based static task scheduling for heterogeneous embedded systemsThe Journal of Supercomputing10.1007/s11227-021-03887-178:1(279-314)Online publication date: 1-Jan-2022
https://dl.acm.org/doi/10.1007/s11227-021-03887-1
Khasanov RRobledo JMenard CGoens ACastrillon J(2021)Domain-specific Hybrid Mapping for Energy-efficient Baseband Processing in Wireless NetworksACM Transactions on Embedded Computing Systems10.1145/347699120:5s(1-26)Online publication date: 17-Sep-2021
https://dl.acm.org/doi/10.1145/3476991
Menard CGoens AHempel GKhasanov RRobledo JTeweleitt FCastrillon J(2021)Mocasin—Rapid Prototyping of Rapid Prototyping ToolsProceedings of the 2021 Drone Systems Engineering and Rapid Simulation and Performance Evaluation: Methods and Tools Proceedings10.1145/3444950.3447285(66-73)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3444950.3447285
Letras MFalk JSchwarzer TTeich J(2020)Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and MeasurementsACM Transactions on Design Automation of Electronic Systems10.1145/343181426:3(1-33)Online publication date: 31-Dec-2020
https://dl.acm.org/doi/10.1145/3431814
Zoor MApvrille LPacalet RGuerra EIovino L(2020)SysML modelsProceedings of the 23rd ACM/IEEE International Conference on Model Driven Engineering Languages and Systems: Companion Proceedings10.1145/3417990.3419225(1-10)Online publication date: 16-Oct-2020
https://dl.acm.org/doi/10.1145/3417990.3419225
Show More Cited By

View Options

View options

Media

Figures

Other

Tables

View Issue’s Table of Contents