research-article

StepNP: A System-Level Exploration Platform for Network Processors

Authors:

Pierre Paulin,

Chuck Pilkington,

Essaid BensoudaneAuthors Info & Claims

IEEE Design & Test, Volume 19, Issue 6

Pages 17 - 26

https://doi.org/10.1109/MDT.2002.1047740

Published: 01 November 2002 Publication History

Publisher Site

Abstract

The fast-changing communications market requires high-performance yet flexible network-processingplatforms. StepNP is an exploratory network processor simulation environment for exploring applications, multiprocessor network-processing architectures, and SoC tools. Supporting model interaction, instrumentation, and analysis, the platform lets R&D teams easily add new processors, coprocessors, and interconnects.

References

[1]

N. Shah, Understanding Network Processors, internal report, Dept. of Electrical Eng. and Computer Science, Univ. of California, Berkeley, 2001; http://www-cad.eecs.berkeley.edu/~niraj/papers/UnderstandingNPs.pdf.

Google Scholar

[2]

P.G. Paulin F. Karim and P. Bromley, "Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools," Proc. Design, Automation, and Test in Europe (DATE 01), IEEE CS Press, Los Alamitos, Calif., 2001, pp. 420-429.

Digital Library

Google Scholar

[3]

L. Benini and G. De Micheli, "Networks on Chip: A New SoC Paradigm," Computer, vol. 35, no. 1, Jan. 2002, pp. 70-72.

Digital Library

Google Scholar

[4]

F. Karim, et al., "On-Chip Communication Architecture for OC-768 Network Processors," Proc. Design Automation Conf. (DAC 01), ACM Press, New York, 2001, pp. 678-683.

Digital Library

Google Scholar

[5]

P.G. Paulin and M. Santana, "FlexWare: A Retargetable Embedded-Software Development Environment," IEEE Design & Test of Computers, vol. 19, no. 4, July-Aug. 2002, pp. 59-69.

Digital Library

Google Scholar

[6]

A. Clouard, et al., "Towards Bridging the Gap between SoC Transactional and Cycle-Accurate Levels," Proc. Design, Automation, and Test in Europe Designer Forum, DATE Conf. Secretariat, Edinburgh, UK, 2002, pp. 22-29.

Google Scholar

[7]

E. Kohler, et al., "The Click Modular Router," ACM Trans. Computer Systems, vol. 18, no. 3, Aug. 2000, pp. 263-297.

Digital Library

Google Scholar

[8]

J.L. Hennessy, et al., Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Mateo, Calif., 1990.

Digital Library

Google Scholar

Cited By

View all

Vinco SBombieri NPagliari DFummi FMacii EPoncino M(2019)A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing MonitorsACM Transactions on Design Automation of Electronic Systems10.1145/330856524:3(1-23)Online publication date: 11-Mar-2019
https://dl.acm.org/doi/10.1145/3308565
Guarnieri VPetricca MSassone AVinco SBombieri NFummi FMacii EPoncino MFettweis GNebel W(2014)A cross-level verification methodology for digital IPs augmented with embedded timing monitorsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616978(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616978
Hatami NBaranowski RPrinetto PWunderlich H(2014)Multilevel Simulation of Nonfunctional Properties by Piecewise EvaluationACM Transactions on Design Automation of Electronic Systems10.1145/264795519:4(1-21)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2647955
Show More Cited By

Index Terms

StepNP: A System-Level Exploration Platform for Network Processors

Recommendations

Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs
CASES '04: Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems

In this paper, we propose a power/performance estimation layer designed for StepNP, a system-level architecture simulation and exploration platform for Network Processors and Multi-Processor Systems-on-Chip (MP-SoCs). The first goal of our work is to ...
Flattened Butterfly Topology for On-Chip Networks

With the trend towards increasing number of cores in a multicore processors, the on-chip network that connects the cores needs to scale efficiently. In this work, we propose the use of high-radix networks in on-chip networks and describe how the ...
A High-Throughput Distributed Shared-Buffer NoC Router

Microarchitectural configurations of buffers in routers have a significant impact on the overall performance of an on-chip network (NoC). This buffering can be at the inputs or the outputs of a router, corresponding to an input-buffered router (IBR) or ...

Comments

Information & Contributors

Information

Published In

IEEE Design & Test Volume 19, Issue 6

November 2002

120 pages

ISSN:0740-7475

Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 November 2002

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

51
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 28 Jul 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Vinco SBombieri NPagliari DFummi FMacii EPoncino M(2019)A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing MonitorsACM Transactions on Design Automation of Electronic Systems10.1145/330856524:3(1-23)Online publication date: 11-Mar-2019
https://dl.acm.org/doi/10.1145/3308565
Guarnieri VPetricca MSassone AVinco SBombieri NFummi FMacii EPoncino MFettweis GNebel W(2014)A cross-level verification methodology for digital IPs augmented with embedded timing monitorsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616978(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616978
Hatami NBaranowski RPrinetto PWunderlich H(2014)Multilevel Simulation of Nonfunctional Properties by Piecewise EvaluationACM Transactions on Design Automation of Electronic Systems10.1145/264795519:4(1-21)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2647955
Tafesse BMuthukumar V(2013)Framework for simulation of heterogeneous MpSoC for design space explorationVLSI Design10.1155/2013/9361812013(11-11)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1155/2013/936181
Holt JDastidar JLindberg DPape JYang P(2012)A full lifecycle performance verification methodology for multicore systems-on-chipACM Transactions on Design Automation of Electronic Systems10.1145/2209291.220929417:3(1-18)Online publication date: 5-Jul-2012
https://dl.acm.org/doi/10.1145/2209291.2209294
Ventroux NSassolas TGuerre ACreusillet BKeryell RPérez DNiar SSilvano CAbhari M(2012)SESAM/Par4AllProceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2162131.2162133(9-16)Online publication date: 23-Jan-2012
https://dl.acm.org/doi/10.1145/2162131.2162133
Raina AMuthukumar V(2011)A unified design space simulation environment for network-on-chip: fuse-NInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2011.0380553:1(23-32)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1504/IJHPSA.2011.038055
Schliecker SErnst R(2011)Real-time performance analysis of multiprocessor systems with shared memoryACM Transactions on Embedded Computing Systems10.1145/1880050.188005810:2(1-27)Online publication date: 7-Jan-2011
https://dl.acm.org/doi/10.1145/1880050.1880058
Shen HPétrot FLin Y(2010)A flexible hybrid simulation platform targeting multiple configurable processors SoCProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899754(155-160)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899754
Schliecker SNegrean MErnst RDe Micheli GAl-Hashimi BMueller WMacii E(2010)Bounding the shared resource load for the performance analysis of multiprocessor systemsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871108(759-764)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871108
Show More Cited By

Abstract

References

Cited By

Index Terms

Recommendations

Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs

Flattened Butterfly Topology for On-Chip Networks

A High-Throughput Distributed Shared-Buffer NoC Router

Comments

Information

Published In

Publisher

Publication History

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations