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Framework for simulation of heterogeneous MpSoC for design space exploration

Authors:

Bisrat Tafesse,

Venkatesan MuthukumarAuthors Info & Claims

VLSI Design, Volume 2013

Article No.: 11, Page 11

https://doi.org/10.1155/2013/936181

Published: 01 January 2013 Publication History

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Abstract

Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes amodular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using System C/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios.

References

[1]

L. Thiele, I. Bacivarov, W. Haid, and K. Huang, "Mapping applications to tiled multiprocessor embedded systems," in Proceedings of the 7th International Conference on Application of Concurrency to System Design (ACSD '07), pp. 29-40, July 2007.

Digital Library

[2]

C. Neeb and N. Wehn, "Designing efficient irregular networks for heterogeneous systems-on-chip," Journal of Systems Architecture, vol. 54, no. 3-4, pp. 384-396, 2008.

Digital Library

[3]

S. Manolache, P. Eles, and Z. Peng, Real-Time Applications with Stochastic Task Execution Times, Analysis and Optimization, Springer, 1st edition, 2007.

Digital Library

[4]

W. Wolf, High-Performance Embedded Computing, Elsevier, 2007.

Digital Library

[5]

A. A. Jerraya and W. Wolf, Multiprocessor Systems-on-Chips, Morgan Kaufmann Series in Systems on Silicon, 2005.

[6]

J. Nurmi, H. Tenhunen, J. Isoaho, and A. Jantsch, Interconnect-Centric Design for Advanced SoC and NoC, Kluwer Academic, 2004.

[7]

N. D. Thai, "Real-time scheduling in distributed systems," in Proceedings of the IEEE International Conference on Parallel Computing in Electrical Engineering (PARELEC '02), pp. 165- 170, 2002.

Digital Library

[8]

R. Marculescu, U. Y. Ogras, L. S. Peh, N. E. Jerger, and Y. Hoskote, "Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 3-21, 2009.

Digital Library

[9]

G. DeMicheli and L. Benini, Networks on Chips: Technology and Tools Systems on Silicon, Academic Press, 2006.

[10]

R. Marculescu and P. Bogdan, "The Chip is the network: toward a science of network-on-chip design," Foundations and Trends in Electronic Design Automation, vol. 2, no. 4, pp. 371-461, 2007.

Digital Library

[11]

S. Stuijk, T. Basten, M. Geilen, A. H. Ghamarian, and B. Theelen, "Resource-efficient routing and scheduling of time-constrained network-on-chip communication," in Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD '06), pp. 45-52, September 2006.

[12]

J. Hu and R. Marculescu, "Communication and task scheduling of application-specific networks-on-chip," Proceedings of the IEEE, vol. 152, no. 5, pp. 643-651, 2005.

[13]

G. Varatkar and R. Marculescu, "Communication-aware task scheduling and voltage selection for total systems energy minimization," in International Conference on Computer Aided Design (ICCAD '03), pp. 510-517, San Jose, Calif, USA, November 2003.

Digital Library

[14]

S. Zhang, K. S. Chatha, and G. Konjevod, "Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules," in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'07), pp. 225-230, August 2007.

Digital Library

[15]

F. Gruian, "Hard real-time scheduling for low-energy using stochastic data and DVS processors," in Proceedings of the International Symposium on Low Electronics and Design (ISLPED '01), pp. 46-51, August 2001.

Digital Library

[16]

M. T. Schmitz, B. M. Al-Hashimi, and P. Eles, "Iterative schedule optimization for voltage scalable distributed embedded systems," Journal ACM Transactions on Embedded Computing Systems, vol. 3, no. 1, pp. 182-217, 2004.

Digital Library

[17]

D. Shin and J. Kim, "Power-aware communication optimization for networks-on-chips with voltage scalable links," in International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '04), pp. 170-175, September 2004.

Digital Library

[18]

E. Carvalho, N. Calazans, and F. Moraes, "Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs," in Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), pp. 34-40, May 2007.

Digital Library

[19]

H. J. Ahn, M. H. Cho, M. J. Jung, Y. H. Kim, J. M. Kim, and C. H. Lee, "UbiFOS; a small real-time operating system for embedded systems," ETRI Journal, vol. 29, no. 3, pp. 259-269, 2007.

[20]

C. Ostler and K. S. Chatha, "An ILP formulation for systemlevel application mapping on network processor architectures," in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '07), pp. 99-104, April 2007.

[21]

H. M. Harmanani and R. Farah, "A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area," in Proceedings of the Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA '08), pp. 29-32, June 2008.

[22]

J. Hu and R. Marculescu, "Energy- and performance-aware mapping for regular NoC architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp. 551-562, 2005.

Digital Library

[23]

S. Murali and G. DeMicheli, "Bandwidth-constrained mapping of cores onto NoC architectures," in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '04), pp. 896-901, February 2004.

Digital Library

[24]

P. Poplavko, T. Basten, M. Bekooij, J. Van Meerbergen, and B. Mesman, "Task-level timing models for guaranteed performance in multiprocessor networks-on-chip," in Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '03), pp. 63-72, November 2003.

Digital Library

[25]

G. Ascia, V. Catania, and M. Palesi, "Multi-objective mapping for mesh-based NoC architectures," in Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and System Synthesis (CODES+ISSS '04), pp. 182-187, September 2004.

Digital Library

[26]

K. Srinivasan and K. S. Chatha, "A technique for low energy mapping and routing in network-on-chip architectures," in Proceedings of the International Symposium on Low Power Electronics and Design, pp. 387-392, August 2005.

Digital Library

[27]

P. Brucker, Scheduling Algorithms, 5th edition, 2006.

Digital Library

[28]

X. Zhu and W. Qin, "Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery," in Proceedings of the 43rd Annual Design Automation Conference (DAC '06), pp. 53-56, 2006.

Digital Library

[29]

R. Holsmark, M. Palesi, and S. Kumar, "Deadlock free routing algorithms for mesh topology NoC systems with regions," in Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD '06), pp. 696-703, September 2006.

[30]

M. Pirretti, G. M. Link, R. R. Brooks, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "Fault tolerant algorithms for network-on-chip interconnect," in Proceedings of the IEEE Computer Society Annual Symposiumon VLSI: Emerging Trends in VLSI Systems Design, pp. 46-51, February 2004.

[31]

D. Bertozzi, L. Benini, and G. De Micheli, "Error control schemes for on-chip communication links: the energyreliability tradeoff," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 6, pp. 818- 831, 2005.

Digital Library

[32]

F. Angiolini, D. Atienza, S. Murali, L. Benins, and G. DeMicheli, "Reliability support for on-chip memories using Networks-on-Chip," in Proceedings of the 24th International Conference on Computer Design (ICCD '06), pp. 389-396, October 2006.

[33]

V. Puente, J. A. Gregorio, F. Vallejo, and R. Beivide, "Immunet: a cheap and robust fault-tolerant packet routing mechanism," in Proceedings of the 31st Annual International Symposium on Computer Architecture, pp. 198-209, June 2004.

Digital Library

[34]

A. Pullini, F. Angiolini, D. Bertozzi, and L. Benini, "Fault tolerance overhead in network-on-chip flow control schemes," in proceedings of the 18th Symposium on Integrated Circuits and Systems Design (SBCCI '05), pp. 224-229, September 2005.

Digital Library

[35]

P. Beerel and M. E. Roncken, "Low power and energy efficient asynchronous design," Journal of Low Power Electronics, vol. 3, no. 3, pp. 234-253, 2007.

[36]

M. Koibuchi, H. Matsutani, H. Amano, and T. M. Pinkston, "A lightweight fault-tolerant mechanism for network-on-chip," in Proceedings of the 2nd IEEE International Symposium on Networks-on-Chip (NOCS '08), pp. 13-22, April 2008.

Digital Library

[37]

P. Bogdan, T. Dumitraş, and R. Marculescu, "Stochastic communication: a new paradigm for fault-tolerant Networks-onchip," VLSI Design, vol. 2007, Article ID 95348, 17 pages, 2007.

[38]

S. Murali and G. De Micheli, "SUNMAP: a tool for automatic topology selection and generation for NoCs," in Proceedings of the 41st Design Automation Conference (DAC '04), pp. 914-919, June 2004.

Digital Library

[39]

A. Jalabert, S. Murali, L. Benini, and G. De Micheli, "Xpipescompiler: a tool for instantiating application specific networks on chip," in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '04), pp. 884-889, February 2004.

[40]

Z. Lu, R. Thid, M. Millberg, E. Nilsson, and A. Jantsch, "NNSE: nostrumnetwork-on-chip simulation environment," in Proceedings of the Swedish System-on-Chip Conference (SSoCC '03), April 2005.

[41]

S. Mahadevan, M. Storgaard, J. Madsen, and K. Virk, "ARTS: a system-level framework for modeling MPSoC components and analysis of their causality," in Proceedings of the 13th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems (MASCOTS '05), pp. 480-483, September 2005.

[42]

P. G. Paulin, C. Pilkington, and E. Bensoudane, "StepNP: a system-level exploration platform for network processors," IEEE Design and Test of Computers, vol. 19,no. 6, pp. 17-26,2002.

Digital Library

[43]

N. Genko, D. Atienza, G. De Micheli, J. M. Mendias, R. Hermida, and F. Catthoor, "A complete network-on-chip emulation framework," in Proceedings of the Design, Automation and Test in Europe (DATE '05), pp. 246-251, March 2005.

[44]

M. Coppola, S. Curaba, M. D. Grammatikakis, G. Maruccia, and F. Papariello, "OCCN: a network-on-chip modeling and simulation framework," in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, DATE 04, vol. 3, pp. 174-179, February 2004.

[45]

C. A. Zeferino and A. A. Susin, "SoCIN: a parametric and scalable Network-on-Chip," in Proceedings of the 16th Symposium on Integrated Circuits and Systems Design, pp. 169-174, 2003.

Digital Library

[46]

H. Orsila, E. Salminen, M. Hännikäinen, and T. D. Hämäläinen, "Evaluation of heterogeneous multiprocessor architectures by energy and performance optimization," in Proceedings of the International Symposium on System-on-Chip (SOC '08), pp. 1- 6, November 2008.

[47]

H. Orsila, T. Kangas, E. Salminen, T. D. Hämäläinen, and M. Hännikäinen, "Automated memory-aware application distribution for Multi-processor System-on-Chips," Journal of Systems Architecture, vol. 53, no. 11, pp. 795-815, 2007.

Digital Library

[48]

F. Paterna, L. Benini, A. Acquaviva, F. Papariello, and G. Desoli, "Variability-tolerant workload allocation for MPSoC energy minimization under real-time constraints," in Proceedings of the IEEE/ACM/IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia '09), pp. 134-142, October 2009.

Digital Library

[49]

R. Teodorescu and J. Torrellas, "Variation-aware application scheduling and power management for chip multiprocessors," ACM SIGARCH Computer Architecture News, vol. 36, no. 3, pp. 363-374, 2008.

[50]

Z. Lide, L. S. Bai, R. P. Dick, S. Li, and R. Joseph, "Process variation characterization of chip-level multiprocessors," in Proceedings of the 46th ACM/IEEE Design Automation Conference (DAC '09), pp. 694-697, New York, NY, USA, July 2009.

Digital Library

[51]

"Embedded System Synthesis Benchmarks Suite (E3S)," http://ziyang.eecs.umich.edu/~dickrp/e3s/.

[52]

C. Ababei and R. Katti, "Achieving network on chip fault tolerance by adaptive remapping," in Proceedings of the 23rd IEEE International Parallel and Distributed Processing Symposium (IPDPS '09), pp. 23-29, May 2009.

Digital Library

[53]

O. Derin, D. Kabakci, and L. Fiorin, "Online task remapping strategies for fault-tolerant network-on-chip multiprocessors," in Proceedings of the 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS '11), pp. 129-136, May 2011.

Digital Library

[54]

"Standard Task Graph (STG)," http://www.kasahara.elec.waseda.ac.jp/schedule/.

Cited By

Belkacemi DDaoui MBouzefrane SBouchebaba Y(2019)Parallel Applications Mapping onto Network on Chip Based on Heterogeneous MPSoCs Using Hybrid AlgorithmsInternational Journal of Distributed Systems and Technologies10.4018/IJDST.201904010310:2(37-63)Online publication date: 1-Apr-2019
https://dl.acm.org/doi/10.4018/IJDST.2019040103
Sirkunan JOoi CShaikh-Husin NHau YMarsono M(2017)Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platformsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2016.12.00673:C(42-52)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1016/j.sysarc.2016.12.006

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Framework for simulation of heterogeneous MpSoC for design space exploration

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Published In

cover image VLSI Design

VLSI Design Volume 2013, Issue

January 2013

228 pages

ISSN:1065-514X

EISSN:1563-5171

Issue’s Table of Contents

Publisher

Hindawi Limited

London, United Kingdom

Publication History

Accepted: 14 April 2013

Revised: 29 January 2013

Published: 01 January 2013

Received: 08 October 2012

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Cited By

Belkacemi DDaoui MBouzefrane SBouchebaba Y(2019)Parallel Applications Mapping onto Network on Chip Based on Heterogeneous MPSoCs Using Hybrid AlgorithmsInternational Journal of Distributed Systems and Technologies10.4018/IJDST.201904010310:2(37-63)Online publication date: 1-Apr-2019
https://dl.acm.org/doi/10.4018/IJDST.2019040103
Sirkunan JOoi CShaikh-Husin NHau YMarsono M(2017)Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platformsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2016.12.00673:C(42-52)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1016/j.sysarc.2016.12.006

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