article

Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors

Authors:

Radu Teodorescu,

Josep TorrellasAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 36, Issue 3

Pages 363 - 374

https://doi.org/10.1145/1394608.1382152

Published: 01 June 2008 Publication History

Abstract

Within-die process variation causes individual cores in a ChipMultiprocessor (CMP) to differ substantially in both static powerconsumed and maximum frequency supported. In this environment,ignoring variation effects whenscheduling applications or when managing power withDynamic Voltage and Frequency Scaling (DVFS) is suboptimal. This paper proposes variation-aware algorithms for applicationscheduling and power management. One such power managementalgorithm, called {\em LinOpt}, uses linear programmingto find the best voltage and frequency levels for each of thecores in the CMP --- maximizing throughput at a given power budget.In a 20-core CMP, the combination of variation-awareapplication scheduling and {\em LinOpt} increases the averagethroughput by 12--17\% and reduces the average $ED^2$ by 30--38\%--- all relative to using variation-awarescheduling together with a simple extension to Intel's Foxtonpower management algorithm.

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 36, Issue 3

June 2008

449 pages

ISSN:0163-5964

DOI:10.1145/1394608

Issue’s Table of Contents

ISCA '08: Proceedings of the 35th Annual International Symposium on Computer Architecture
June 2008
449 pages
ISBN:9780769531748

Copyright © 2008 Authors.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2008

Published in SIGARCH Volume 36, Issue 3

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Hernández PCostero LOlcoz KIgual F(2022)Applying Game-Learning Environments to Power Capping Scenarios via Reinforcement LearningCloud Computing, Big Data & Emerging Topics10.1007/978-3-031-14599-5_7(91-106)Online publication date: 5-Aug-2022
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